Mitsubishi Electric MELSEC Q Series User Manual page 168

• Auto refresh between QCPUs
Figure 4.22 shows program examples between the High Performance model QCPU when Auto refresh
settings in Multiple CPU settings are made as Table4.5.
<Parameter setting>
Setting No. CPU No.
CPU No. 1
Setting 1
CPU No. 2
Transmission side program (CPU No.1)
Write
(Transmission side (CPU No.1))
command
1)
M0 D0.0 D1024.0
Set send data from
D0 to D1023.
6)
D0.0 D1024.0
1) CPU No. 1 creates send data.
2) CPU No. 1 turns on the data setting completion bit.
<Auto refresh execution between multiple CPUs>
3) CPU No. 2 detects the completion of send data setting.
4) CPU No. 2 performs receive data processing.
5) CPU No. 2 turns on the completion of receive data processing.
<Auto refresh execution between multiple CPUs>
CPU No. 1 detects the completion of the receive data processing and turns off the data setting
6)
completion bit.
<Auto refresh execution between multiple CPUs>
7) CPU No. 2 detects that the data setting complete bit turns off, and turns off the receive data processing
completion.
Table4.5 Parameter setting example for interlock program
CPU shared memory
Number of
points
1024
1024
In the parameter setting above, use D0.0 as an interlock device of CPU No.1 (data
setting complete bit) and D1024.0 as an interlock device of CPU No.2 (receive data
processing complete bit).
2)
SET D0.0
RST D0.0
RST M0
Figure 4.22 Interlock program example
CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES
Start End
0000 03FF
0000 03FF
Reception side program (CPU No.2)
(Reception side (CPU No.2))
3)
4)
D0.0 D1024.0
Read receive data
from D0 to D1023.
5)
SET D1024.0
7)
D0.0 D1024.0
RST D1024.0
Device at CPU
Start End
D0 D1023
D1024 D2047
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