Page 1 MITSUBISHI ELECTRIC Programmable Controller User's Manual (Multiple CPU System) QCPU 01 12 2008 INDUSTRIAL AUTOMATION MITSUBISHI ELECTRIC SH(NA)-080485ENG Version H...
Page 4: Safety Precautions
SAFETY PRECAUTIONS (Read these precautions before using this product.) Before using this product, please read this manual and the relevant manuals carefully and pay full attention to safety to handle the product correctly. In this manual, the safety precautions are classified into two levels: " DANGER"...
Page 5 [Design Precautions] DANGER Configure safety circuits external to the programmable controller to ensure that the entire system operates safely even when a fault occurs in the external power supply or the programmable controller. Failure to do so may result in an accident due to an incorrect output or malfunction. (1) Configure external safety circuits, such as an emergency stop circuit, protection circuit, and protective interlock circuit for forward/reverse operation or upper/lower limit positioning.
Page 6 [Design Precautions] DANGER In an output module, when a load current exceeding the rated current or an overcurrent caused by a load short-circuit flows for a long time, it may cause smoke and fire. To prevent this, configure an external safety circuit, such as a fuse. Configure a circuit so that the programmable controller is turned on first and then the external power supply.
Page 7: Installation Precautions
[Installation Precautions] CAUTION Use the programmable controller in an environment that meets the general specifications in the QCPU User's Manual (Hardware Design, Maintenance and Inspection). Failure to do so may result in electric shock, fire, malfunction, or damage to or deterioration of the product.
Page 8 [Wiring Precautions] DANGER Shut off the external power supply for the system in all phases before wiring. Failure to do so may result in electric shock or damage to the product. After wiring, attach the included terminal cover to the module before turning it on for operation. Failure to do so may result in electric shock.
Page 9 [Wiring Precautions] DANGER A protective film is attached to the top of the module to prevent foreign matter, such as wire chips, from entering the module during wiring. Do not remove the film during wiring. Remove it for heat dissipation before system operation. Mitsubishi programmable controllers must be installed in control panels.
Page 10 [Startup and Maintenance Precautions] CAUTION Before performing online operations (especially, program modification, forced output, and operation status change) for the running CPU module from the peripheral connected, read relevant manuals carefully and ensure the safety. Improper operation may damage machines or cause accidents. Do not disassemble or modify the modules.
Page 11 [Disposal Precautions] CAUTION When disposing of this product, treat it as industrial waste. When disposing of batteries, separate them from other wastes according to the local regulations. (For details of the Battery Directive in EU countries, refer to the QCPU User's Manual (Hardware Design, Maintenance and Inspection).) [Transportation Precautions] CAUTION...
Page 12: Revisions
This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent licenses. Mit- subishi Electric Corporation cannot be held responsible for any problems involving industrial property rights which may occur as a result of using the contents noted in this manual. 2008 MITSUBISHI ELECTRIC CORPORATION A - 9...
Page 13 Print date Manual number Revision May, 2008 SH(NA)-080485ENG-G Addition of Universal model QCPU and Process CPU models Model addition Q02PHCP, Q06PHCPU, Q03UDECPU, Q04UDEHCPU, Q06UDEHCPU, Q13UDEHCPU, Q26UDEHCPU Partial correction A term "MELSECNET/G" has been revised to "CC-Link IE controller network" through this manual, GENERIC TERMS AND ABBREVIATIONS, Chapter 1, Section 1.1, 2.1.1, 2.1.2, 2.1.3, 2.2, 2.3, 2.4, 3.1, 3.8, 4.2, 4.3.1, 4.3.3, 5.1, 5.2, 6.1 Dec., 2008...
Page 14: Introduction
INTRODUCTION This manual is designed for users to understand the multiple CPU system including information of the system configuration, functions, and communication with external devices that are required when the MELSEC-Q series programmable controller is used in the multiple CPU system. This manual is composed of the following parts and explains: 1) Chapter 1 and 2 Overview and system configuration of the multiple CPU system...
Page 15: Table Of Contents
CONTENTS SAFETY PRECAUTIONS........................A - 1 REVISIONS ............................A - 9 INTRODUCTION ........................... A - 11 MANUALS ............................. A - 15 MANUAL PAGE ORGANIZATION ......................A - 18 GENERIC TERMS AND ABBREVIATIONS ..................A - 20 CHAPTER1 OUTLINE 1-1 to 1-23 1 - 1 What is multiple CPU system?....................
Page 16 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 4-1 to 4-56 4 - 3 Communications between CPU modules using CPU shared memory ........4 - 3 4.1.1 CPU shared memory......................4 - 8 4.1.2 Communication by auto refresh using CPU shared memory ..........4 - 23 4.1.3 Communication by auto refresh using multiple CPU high speed transmission area..
Page 17 8.2.1 Parameter setting for the Basic model QCPU,High Paformance model QCPU, ....................8 - 3 Process CPU 8 - 15 8.2.2 Parameter setting for the Universal model QCPU ............8 - 23 8.2.3 Reusing preset multiple CPU parameters ................. 8 - 28 Communication program examples using auto refresh ............
Page 18: Manuals
MANUALS To understand the main specifications, functions, and usage of the CPU module, refer to the basic manuals. Read other manuals as well when using a different type of CPU module and its functions. Order each manual as needed, referring to the following lists. The numbers in the "CPU module"...
Page 19 CPU module Manual name Description < Manual number (model code) > QCPU (Q Mode) Programming Manual Programming methods using structured lan- (Structured Text) guages < SH-080366E (13JF68) > QCPU (Q Mode) / QnACPU Programming Man- ual (PID Control Instructions) Dedicated instructions for PID control <...
Page 20 Other relevant manuals Manual name Description CC-Link IE Controller Network Reference Specifications, procedures and settings before system operation, parameter Manual setting, programming, and troubleshooting of the CC-Link IE controller network module < SH-080668ENG (13JV16) > Q Corresponding MELSECNET/H Network Specifications, procedures and settings before system operation, parameter System Reference Manual (PLC to PLC setting, programming, and troubleshooting of a MELSECNET/H network network)
Page 21: Manual Page Organization
MANUAL PAGE ORGANIZATION Note (icon) Reference Chapter The section in this manual or The detailed explanation of "Note . " is The chapter of the current page can be another relevant manual that can provided under the corresponding easily identified by this indication on the be referred to is shown with "Note .
Page 22 In addition, this manual uses the following types of explanations. In addition to description of the page, notes or functions that require special attention are described here. Remark The reference related to the page or useful information are described here. A - 19...
Page 23: Generic Terms And Abbreviations
GENERIC TERMS AND ABBREVIATIONS Unless otherwise specified, this manual uses the following generic terms and abbreviations. indicates a part of the model or version. (Example): Q33B, Q35B, Q38B, Q312B Q3 B Generic term/abbreviation Description Series Q series Abbreviation for Mitsubishi MELSEC-Q series programmable controller Generic term for compact types of Mitsubishi MELSEC-A Series Programmable AnS series Controller...
Page 24 Generic term/abbreviation Description Multiple CPU high speed main Another name for the Q3 DB base unit Base unit model Generic term for the Q33B, Q35B, Q38B, and Q312B main base units Q3 B Generic term for the Q32SB, Q33SB, and Q35SB slim type main base units Q3 SB Another name for the Q38RB redundant power main base unit Q3 RB...
Page 25 Generic term/abbreviation Description Generic term for the QC05B, QC06B, QC12B, QC30B, QC50B, and QC100B Extension cable extension cables Generic term for the QC10TR and QC30TR tracking cables for the Redundant Tracking cable module Generic term for the Q6BAT, Q7BAT, and Q8BAT CPU module batteries, Battery Q2MEM-BAT, SRAM card battery, and Q3MEM-BAT SRAM card battery Generic term for Mitsubishi Graphic Operation Terminal, GOT-A*** series, GOT-F***...
Page 26: What Is Multiple Cpu System?
CHAPTER1 OUTLINE CHAPTER1 OUTLINE 1.1 What is multiple CPU system? (1) Configuration of multiple CPU system A multiple CPU system is a system in which more than one CPU module are mounted on several a main base unit in order to control the I/O modules and intelligent function modules. Motion CPU QCPU PC CPU...
Page 27 (2) Available CPU modules in multiple CPU system Table1.1 shows the available CPU modules in multiple CPU system. Refer to Section 2.3 for the compatible version of each module. Table1.1 Applicable CPU modules CPU module Model Basic model QCPU Q00CPU, Q01CPU Q02CPU,Q02HCPU,Q06HCPU,Q12HCPU, High Performance model QCPU Q25HCPU...
Page 28 CHAPTER1 OUTLINE (3) Method for controlling I/O module and intelligent function module It is necessary to set (control CPU setup) which CPU modules are to control which I/O modules and intelligent function modules with a multiple CPU system. Slot number Control CPU setting Control with CPU module 1.
Page 29 (4) Multiple CPU system setting For control in the multiple CPU system, it is necessary to set up the "Number of mounted CPU modules" and the "Control CPU" with PLC parameter for all CPU modules mounted on the main base unit. User's Manual (Function Explanation, Program Fundamentals) for the CPU module used (5) Access range of multiple CPU system In the multiple CPU system, the access ranges are different between the controlled module and the non-con-...
Page 30: Features Of Multiple Cpu System
CHAPTER1 OUTLINE 1.2 Features of multiple CPU system (1) Multi-control system (a) Configuration optimum for system Since each system uses not only one QCPU but any combinations of the QCPU, Motion CPU, and PC CPU module according to the system, the development efficiency and ease of maintenance of the system can be enhanced.
Page 31 Interaction with a motion controller for motion control is enhanced in the Universal model QCPU. (a) Speeding up data transfer between multiple CPUs Maximum 14 k word-data and a sequence program can be transferred between multiple CPUs with parallel processing. It enables high-speed data transfer independent of scan time, which leads to takt time shortening of equipment.
Page 32 CHAPTER1 OUTLINE (b) Enabling synchronous processing with a motion control An interrupt program which is synchronized with the operation cycle of a motion controller (multiple CPU syn- chronous interrupt program) can be executed. Command I/O from a motion controller can be synchronized with the operation cycle of the motion controller, which enables high-speed data transfer independent of scan time.
Page 33 (c) Timing of data send/receive between the CPU modules can be checked The sampling trace function of the Universal model QCPU enables to check the data send/receive timing with the Motion controller. (Timing of data send/receive can be checked between the Universal model QCPUs.) Using the sampling trace function facilitates to check the data send/receive timing between CPU modules, and reduces the debug time of the multiple CPU system.
Page 34 CHAPTER1 OUTLINE (3) System configuration based on load distribution. (a) Distribution of processing By distributing the high-load processing performed on a single QCPU over several CPU modules, it is possible to reduce the overall system scan time. (Control in 1ms or less) (Control in several to several dozen ms) Data processing (low speed) CPU module for machine control...
Page 35 (5) Communication between CPU modules in the multiple CPU system The following data transfer can be made between CPU modules in the multiple CPU system. (a) Data transfer between CPU modules The following data transfer can be made between CPU modules in the multiple CPU system. (b) Reading data in another CPU The QCPU can read data in another CPU with the following instruction when necessary.
Page 36: Difference From Single Cpu System
CHAPTER1 OUTLINE 1.3 Difference from Single CPU System Differences between the single CPU system and the multiple CPU system are described in this section. Refer to the manuals below for the single CPU system. QCPU User's Manual (Hardware Design, Maintenance and Inspection) User's Manual (Function Explanation, Program Fundamentals) for the CPU module used (1) When using the Basic model QCPU Table1.2 Difference from single CPU system...
Page 37 Table1.2 Difference from single CPU system (continued) Item Single CPU system Multiple CPU system Reference CPU slot = CPU No. 1 CPU module mounting posi- CPU slot only (no CPU No.) Slot 0 = CPU No. 2 Section 3.1.1 tion and CPU No. Slot 1 = CPU No.
Page 38 CHAPTER1 OUTLINE Table1.2 Difference from single CPU system (continued) Item Single CPU system Multiple CPU system Reference Basic model QCPU = 320 points Motion CPU = 2048 points Communication using CPU C Controller module = 2048 points shared memory by auto Not available Section 4.1.2 PC CPU module = 2048 points...
Page 39 (2) When using the High Performance model QCPU Table1.3 Difference from single CPU system Item Single CPU system Multiple CPU system Reference Maximum number of exten- 7 stages sion stages Maximum number of mount- *1,*2 able 65 - (No. of CPUs) I/O modules Q3 B, Q3 SB, Q3 RB, Q3 DB Main base unit model...
Page 40 CHAPTER1 OUTLINE Table1.3 Difference from single CPU system (continued) Item Single CPU system Multiple CPU system Reference CPU slot = CPU No. 1 CPU module mounting posi- Slot 0 = CPU No. 2 CPU slot only (no CPU No.) Section 3.1.2 tion and CPU No.
Page 41 Table1.3 Difference from single CPU system (continued) Single CPU system Multiple CPU system Reference Communication using CPU Up to 2k words in total of 4 settings per shared memory by auto Not available CPU. The total for all CPU modules is Section 4.1.2 refresh 8k words.
Page 42 CHAPTER1 OUTLINE (3) When using the Process CPU Table1.4 Difference from single CPU system Item Single CPU system Multiple CPU system Reference Maximum number of exten- 7 stages sion stages Maximum number of mount- able 65 - (No. of CPUs) I/O modules Q3 B, Q3 RB, Q3 DB Main base unit model...
Page 43 Table1.4 Difference from single CPU system (continued) Item Single CPU system Multiple CPU system Reference CPU slot = CPU No. 1 CPU module mounting posi- CPU slot only Slot 0 = CPU No. 2 Section 3.1.2 tion and CPU No. (no CPU No.) Slot 1 = CPU No.
Page 44 CHAPTER1 OUTLINE Table1.4 Difference from single CPU system (continued) Item Single CPU system Multiple CPU system Reference Communication using CPU Up to 2k words in total of 4 settings per shared memory by auto Not available CPU. The total for all CPU modules is Section 4.1.2 refresh 8k words.
Page 45 (4) When using the Universal model QCPU Table1.5 Difference from single CPU system Item Single CPU system Multiple CPU system Reference Maximum number of exten- 7 stages (when the Q00UCPU, Q01UCPU, Q02UCPU is used:4 stages) sion stages *1,*2 65 - (Number of CPUs) Maximum number of mount- 64(Use of Q00UCPU and (Use of Q00UCPU and Q01UCPU:25-...
Page 46 CHAPTER1 OUTLINE Table1.5 Difference from single CPU system (continued) Item Single CPU system Multiple CPU system Reference Setting the relations between the CPU Access from CPU module to module and other modules with the All modules can be controlled. Section 3.4 other modules PLC parameter (control CPU) is required.
Page 47 Table1.5 Difference from single CPU system (continued) Item Single CPU system Multiple CPU system Reference Transmission from each CPU module Communication using QCPU is up to 2k words in total of four ranges. standard area by auto Not available Section 4.1.2 The total for all CPU modules is 8k refresh words.
Page 48 CHAPTER1 OUTLINE *1: "No. of CPUs" indicates the number of CPU modules set at "No. of PLC" in the Multiple CPU settings screen of PLC parameter. *2: When the PC CPU module is mounted, the maximum number of mountable I/O modules is the result of "65 - (Number of CPUs + 1) (when using the Q00UCPU, Q01UCPU: 24 - (Number of CPUs + 1)) (when using the Q02UCPU: 37 - (Number of CPUs + 1))".
Page 49: System Configuration
CHAPTER2 SYSTEM CONFIGURATION This chapter explains the system configuration of Multiple CPU Systems, and the precautions for Multiple CPU System configuration. 2.1 System configuration 2.1.1 System configuration using Basic model QCPU (Q00CPU, Q01CPU) This following explains the system configuration using the Basic model QCPU. (1) System using the main base unit (Q3 B) (a) System configuration Battery for...
Page 50 CHAPTER2 SYSTEM CONFIGURATION When the multiple CPU system is configured using the Basic model QCPU as the CPU No.1, only the following CPU modules can be used as the CPUs No.2 and 3. • Motion CPU(Q172CPUN(-T), Q173CPUN(-T), Q172HCPU(-T), Q173HCPU(-T)) • PC CPU module •...
Page 51 (b) Outline of system configuration Main base unit..32-point modules are mounted on each slot. Q38B (8 slots occupied) ..Slot number ..I/O number Empty space of 16 points Q series power CPU module 3 supply module CPU module 2 CPU module 1 Extension base unit ..32-point modules are mounted on each slot.
Page 52 CHAPTER2 SYSTEM CONFIGURATION Table2.1 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU1: CPU No. 1 (Basic model QCPU), CPU2: CPU No. 2 (Motion CPU), CPU number CPU3: CPU No.3 (PC CPU module/C Controller module) Maximum number of 4 extension units extension stages...
Page 53 (2) When using the slim type main base unit (Q3 SB) (a) System configuration Battery for QCPU (Q6BAT) Basic model C Controller QCPU module Slim type main base unit * Slim type power supply/input/output/intelligent function module The slim type main base unit does not have an extension cable connector. The extension base unit and GOT cannot be bus-connected.
Page 54 CHAPTER2 SYSTEM CONFIGURATION (b) Outline of system configuration Slim type main base unit 32-point modules are mounted on each slot. Q35SB (5 slots occupied) Slot number PULL I/O number Slim type power supply CPU module 2 module CPU module 1 Figure 2.4 System configuration example for using Q3 Table2.2 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU number...
Page 55 (3) When using the Multiple CPU High speed main base unit (Q3 DB) (a) System configuration Battery for QCPU (Q6BAT) PC CPU Basic model C Controller module * QCPU module * DB type multiple CPU high speed main base unit * Extension cable Q series power supply/input/output/intelligent function module...
Page 56 CHAPTER2 SYSTEM CONFIGURATION (b) Outline of system configuration Main base unit..32-point modules are mounted on each slot. Q38DB (8 slots occupied) ..Slot number ..I/O number Q series power Empty space of 16 points supply module CPU module 2 * CPU module 1 Extension base unit ..32-point modules are mounted on each slot.
Page 57 Table2.3 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU number CPU1: CPU No. 1 (Basic model QCPU), CPU2: CPU No. 2 (PC CPU module C Controller module) Maximum number of 4 extension units extension stages Maximum number of mountable I/O 25 - (No.
Page 58: Cpu No.1
CHAPTER2 SYSTEM CONFIGURATION 2.1.2 System configuration using High Performance model QCPU or Process CPU as CPU No.1 This following explains the system configuration using the High Performance model QCPU and the Process CPU as the CPU No.1. (1) When using the main base unit (Q3 B) (a) System configuration Memory card * High Performance...
Page 59 Only one memory card can be mounted. Select an appropriate memory card from the SRAM, Flash and ATA in accordance with application and capacity. When a commercial memory card is used, the operation is not guaranteed. Use the Q series power supply module for the power supply module. Keep the current consumption within the rated output current of the power supply module.
Page 60 CHAPTER2 SYSTEM CONFIGURATION (b) Outline of system configuration Main base unit..32-point modules are mounted on each slot. Q312B (12 slots occupied) ..Slot number ..I/O number Q series power CPU module 4 CPU module 3 supply module CPU module 2 CPU module 1 Extension base unit ..32-point modules are mounted on each slot.
Page 61 Table2.4 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU number CPU module1: CPU No.1, CPU module 2: CPU No.2, CPU module 3: CPU No.3, CPU module 4: CPU No.4 Maximum number of 7 extension stages extension stages Maximum number of mountable I/O...
Page 62 CHAPTER2 SYSTEM CONFIGURATION (2) When using the redundant power main base unit (Q3 RB) (a) System configuration Memory card * High Performance model QCPU Process CPU Battery for QCPU (Q6BAT) Universal model Q7BAT-SET QCPU RB type redundant power main base unit * Battery holder Battery for QCPU (Q7BAT) Q8BAT-SET...
Page 63 ● When the multiple CPU system is configured using the High Performance model QCPU or the Process CPU as the CPU No.1, only the following modules can be used as the CPUs No.2 to CPU No.4. • High Performance model QCPU •...
Page 64 CHAPTER2 SYSTEM CONFIGURATION (b) Outline of system configuration Redundant main base unit ..32-point module is mounted on each slot. Q38RB (8 slots occupied) ..Slot number ..I/O number CPU module 4 Redundant Power CPU module 3 supply module CPU module 2 CPU module 1 Extension base unit ..32-point modules are mounted on each slot.
Page 65 Table2.5 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU number CPU module1: CPU No.1, CPU module 2: CPU No.2, CPU module 3: CPU No.3, CPU module 4: CPU No.4 Maximum number of 7 extension stages extension stages Maximum number of 65 - (No.
Page 66 CHAPTER2 SYSTEM CONFIGURATION (3) When using the slim type main base unit (Q3 SB) (a) System configuration Memory card * High Performance C Controller model QCPU module * Battery for QCPU (Q6BAT) Universal model Q7BAT-SET QCPU * Slim type main base unit * Battery holder Battery for QCPU (Q7BAT) Q8BAT-SET...
Page 67 (b) Outline of system configuration Slim type main base unit ..32-point module is mounted on each slot. Q35SB(5 slots occupied) ..Slot number ..I/O number Slim type power CPU module 3 supply module CPU module 2 CPU module 1 Figure 2.12 System configuration example for using Q3 SB Table2.6 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU number...
Page 68 CHAPTER2 SYSTEM CONFIGURATION (4) When using the Multiple CPU high speed main base unit (Q3 DB) (a) System configuration Memory card * High Performance PC CPU module C Controller Battery for QCPU (Q6BAT) model QCPU module * Q7BAT-SET Process CPU Universal model QCPU* DB type multiple CPU high speed main...
Page 69 When the multiple CPU system is configured using the High Performance model QCPU or the Process CPU as the CPU No.1, only the following CPU modules can be used as the CPUs No.2 to No.4. • High Performance model QCPU •...
Page 70 CHAPTER2 SYSTEM CONFIGURATION (b) Outline of system configuration Main base unit..32-point modules are mounted on each slot. Q312DB (12 slots occupied) ..Slot number ..I/O number Q series power CPU module 4 supply module CPU module 3 CPU module 2 CPU module 1 Extension base unit ..32-point modules are mounted on each slot.
Page 71 Table2.7 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU number CPU module1: CPU No.1, CPU module 2: CPU No.2, CPU module 3: CPU No.3, CPU module 4: CPU No.4 Maximum number of 7 extension stages extension stages Maximum number of mountable I/O...
Page 72: System Configuration Using Universal Model Qcpu As Cpu No.1
CHAPTER2 SYSTEM CONFIGURATION 2.1.3 System configuration using Universal model QCPU as CPU No.1 The following explains the system configuration using the Universal model QCPU as the CPU No.1. (1) When using the Multiple CPU High speed main base unit (Q3 DB) (a) System configuration Memory card * Battery for QCPU (Q6BAT)
Page 73 Only one memory card can be mounted. Select an appropriate memory card from the SRAM, Flash and ATA in accordance with application and capacity. When a commercial memory card is used, the operation is not guaranteed. Use the Q series power supply module for the power supply module. Keep the current consumption within the rated output current of the power supply module.
Page 74 CHAPTER2 SYSTEM CONFIGURATION (b) Outline of system configuration Main base unit..32-point modules are mounted on each slot. Q312DB (12 slots occupied) ..Slot number ..I/O number Q series power CPU module 4 supply module CPU module 3 CPU module 2 CPU module 1 Extension base unit ..32-point modules are mounted on each slot.
Page 75 Table2.8 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU number CPU module1: CPU No.1, CPU module 2: CPU No.2, CPU module 3: CPU No.3, CPU module 4: CPU No.4 Maximum number of 7 extension stages(when the Q00UCPU, Q01UCPU, Q02UCPU is used: 4 extension stages) extension stages Maximum number of 65 - (No.
Page 76 CHAPTER2 SYSTEM CONFIGURATION (2) When using the main base unit (Q3 B) (a) System configuration Memory card * High Performance Motion PC CPU C Controller Battery for QCPU (Q6BAT) model QCPU CPU* module * module * Q7BAT-SET Process CPU Universal model QCPU Battery holder Battery for QCPU (Q7BAT)
Page 77 ● When the multiple CPU system is configured using Q00UCPU, Q01UCPU, Q02UCPU as the CPU No.1, only the following CPU modules can be used as the CPUs No.2 and No.3. • Motion CPU (Q172CPUN(-T), Q173CPUN(-T), Q172HCPU(-T), and Q173HCPU(-T)) • PC CPU module (PPC-CPU852(MS)-512) •...
Page 78 CHAPTER2 SYSTEM CONFIGURATION (b) Outline of system configuration Main base unit..32-point modules are mounted on each slot. Q312B (12 slots occupied) ..Slot number ..I/O number Q series power CPU module 4 CPU module 3 supply module CPU module 2 CPU module 1 Extension base unit ..32-point modules are mounted on each slot.
Page 79 Table2.9 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU number CPU module1: CPU No.1, CPU module 2: CPU No.2, CPU module 3: CPU No.3, CPU module 4: CPU No.4 Maximum number of 7 extension stages (when the Q02UCPU is used: 4 extension stages) extension stages Maximum number of 65 - (No.
Page 80 CHAPTER2 SYSTEM CONFIGURATION (3) When using the redundant power main base unit (Q3 RB) (a) System configuration Memory card * High Performance model QCPU Process CPU Battery for QCPU (Q6BAT) Universal model Q7BAT-SET QCPU RB type redundant power main base unit * Battery holder Battery for QCPU (Q7BAT) Q8BAT-SET...
Page 81 ● The Q00UCPU, Q01UCPU, Q02UCPU is not available for the multiple CPU system. ● When the multiple CPU system is configured using the Universal model QCPU (except Q00UCPU, Q01UCPU, Q02UCPU) or the Process CPU as the CPU No.1, only the following modules can be used as the CPUs No.2 to CPU No.4.
Page 82 CHAPTER2 SYSTEM CONFIGURATION (b) Outline of system configuration Redundancy main base unit ..32-point module is mounted on each slot. Q38RB (8 slots occupied) ..Slot number ..I/O number CPU module 4 Redundant Power CPU module 3 supply module CPU module 2 CPU module 1 Extension base unit ..32-point modules are mounted on each slot.
Page 83 Table2.10 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU number CPU module1: CPU No.1, CPU module 2: CPU No.2, CPU module 3: CPU No.3, CPU module 4: CPU No.4 Maximum number of 7 extension stages extension stages Maximum number of 65 - (No.
Page 84 CHAPTER2 SYSTEM CONFIGURATION (4) When using the slim type main base unit (Q3 SB) (a) System configuration Memory card * High Performance C Controller model QCPU module * Battery for QCPU (Q6BAT) Universal model Q7BAT-SET QCPU Slim type main base unit * Battery holder Battery for QCPU (Q7BAT) Q8BAT-SET...
Page 85 (b) Outline of system configuration Slim type main base unit ..32-point module is mounted on each slot. Q35SB(5 slots occupied) ..Slot number ..I/O number Slim type power CPU module 3 supply module CPU module 2 CPU module 1 Figure 2.22 System configuration example on using Q3 SB Table2.11 Restrictions on system configuration, available base units, extension cables, and power supply modules CPU number...
Page 86: Configuration Of Peripheral Devices
CHAPTER2 SYSTEM CONFIGURATION 2.2 Configuration of peripheral devices This section describes the system configurations of peripheral devices that can be used with the Basic model QCPU, High Performance model QCPU, Process CPU and Universal model QCPU. For connection between the Motion CPU, PC CPU module or C Controller module and peripheral in the multiple CPU system, refer to the manual of each CPU module.
Page 87 (2) When using the High Performance model QCPU High Performance model QCPU Memory card * PC (GX Developer, GX Configurator) * RS-232 cable Memory card * PC card adapter USB cable * Do not format the ATA card by other than GX Developer. QCPU User's Manual (Hardware Design, Maintenance and Inspection) It is not used for the Q02CPU.
Page 88 CHAPTER2 SYSTEM CONFIGURATION (3) When using the Process CPU Process CPU Memory card * RS-232 cable PC(GX Developer, GX Configurator, PX Developer) * USB cable * Memory card * PC card adapter Do not format the ATA card by other than GX Developer. QCPU User's Manual (Hardware Design, Maintenance and Inspection) For writing into memory card by GX Developer and information on USB cables, refer to the operating manual of the GX Developer.
Page 89 (b) For the Built-in Ethernet port QCPU Universal model QCPU Memory card * Ethernet cable* PC(GX Developer, GX Configurator) * USB cable * Memory card * PC card adapter Do not format the ATA card by other than GX Developer. QCPU User's Manual (Hardware Design, Maintenance and Inspection) For writing into memory card by GX Developer and information on USB cables, refer to the operating manual of the GX Developer.
Page 90: Configurable Device And Available Software
CHAPTER2 SYSTEM CONFIGURATION 2.3 Configurable device and available software Information on devices and software packages used for the system configuration is described in this section. (1) CPU modules available for multiple CPU system There are some restrictions on the CPU module model and function version as shown in the table below. The restriction of each CPU module is explained in Table2.12 to Table2.16.
Page 91 (b) When High Performance model QCPU is used as CPU No.1 Table2.13 Available CPU modules CPU module Model Restrictions Q02CPU, Q02HCPU, Q06HCPU, Function version B High Performance model QCPU Q12HCPU, Q25HCPU Q02PHCPU, Q06PHCPU, Q12PHCPU, Process CPU No version restriction Q25PHCPU Q03UDCPU, Q04UDHCPU, Q06UDHCPU, Q10UDHCPU, Q13UDHCPU, Q20UDHCPU,...
Page 92 CHAPTER2 SYSTEM CONFIGURATION (c) When Process CPU is used as CPU No.1 Table2.14 Available CPU modules CPU module Model Restrictions Q02CPU, Q02HCPU, Q06HCPU, High Performance model QCPU Function version B Q12HCPU, Q25HCPU Q02PHCPU, Q06PHCPU, Q12PHCPU, Process CPU No version restriction Q25PHCPU Q03UDCPU, Q04UDHCPU, Q06UDHCPU, Q10UDHCPU, Q13UDHCPU,...
Page 93 (d) When Universal model QCPU is used as CPU No.1 1) When the Q00UCPU, Q01UCPU, Q02UCPU is used Table2.15 Available CPU modules CPU module Model Restrictions Universal model QCPU Q00UCPU, Q01UCPU, Q02UCPU No version restriction Q172CPUN(-T), Q173CPUN(-T), Refer to the CPU module manual. Motion CPU Q172HCPU(-T), Q173HCPU(-T) The C Controller module whose...
Page 94 CHAPTER2 SYSTEM CONFIGURATION 2) When except the Q00UCPU, Q01UCPU, Q02UCPU is used Table2.16 Available CPU modules CPU module Model Restrictions Q03UDCPU, Q04UDHCPU, Q06UDHCPU, Q10UDHCPU, Q13UDHCPU, Q20UDHCPU, Universal model Q26UDHCPU, Q03UDECPU, No version restriction QCPU Q04UDEHCPU, Q06UDEHCPU, Q10UDEHCPU, Q13UDEHCPU, Q20UDEHCPU, Q26UDEHCPU High Performance Q02CPU, Q02HCPU, Q06HCPU, Function version B or later...
Page 95 (2) Precautions when using Q Series I/O modules and intelligent function modules (a) Compatible I/O modules All I/O modules (QX , QY ) are compatible with the multiple CPU system. They can be used by setting any of CPU No.1 to No.4 as a control CPU. (b) Compatible intelligent function modules 1) The intelligent function modules compatible with the multiple CPU system are those of function version B or later.
Page 96 CHAPTER2 SYSTEM CONFIGURATION (3) Module replaceable online (a) I/O modules and intelligent function modules When a multiple CPU system includes a Process CPU, online module change is allowed. The modules controlled by the Process CPU can be changed online. The modules controlled by the High Performance model QCPU, Motion CPU, PC CPU module and Universal model QCPU cannot be changed online.
Page 97 (4) Applicable software (a) GX Developer and PX Developer Versions of the GX Developer and the PX Developer applicable in the multiple CPU system are shown in Table2.19. Table2.19 Applicable GX Developer and PX Developer Applicable software version QCPU GX Developer PX Developer Version 8.00A or later Basic model QCPU...
Page 98 CHAPTER2 SYSTEM CONFIGURATION (b) Applicable GX Configurator Versions of GX Configurator applicable in the multiple CPU system are shown in Table2.20 Available GX Configurator versions vary depending on the intelligent function module used. For available GX Configurator versions, refer to the manual for the intelligent function module. 1) When Basic model QCPU, Hogh Performance model QCPU, and Process QCPU are used Table2.20 Applicable GX Configurator...
Page 99 2) When Universal model QCPU is used Table2.20 Applicable GX Configurator (continued) Version used in combination with Universal model QCPU Q03UDE/Q04UDEH/ Q02U/Q03UD/ Q00U/Q01U/ Q13UDH/ Q06UDEH/ Product Q04UDH/ Q10UDH/Q20UDH/ Q26UDHCPU Q13UDEH/ Q06UDHCPU in Q10UDEH/ in use Q26UDEHCPU in Q20UDEHCPU Version 8.48A Version 8.62Q Version 8.68W Version 8.78G...
Page 100: Precautions For System Configuration
CHAPTER2 SYSTEM CONFIGURATION 2.4 Precautions for system configuration Restrictions on the system configuration using the Q series CPU module are provided in this section. (1) Modules of restricted quantity The number of mountable modules and supported functions are restricted depending on the module type. For the number of modules that can be mounted for each Motion CPU or PC CPU module, refer to each CPU module manual.
Page 101 (b) When using the High Performance model QCPU, Process CPU Table2.22 Modules of restricted quantity Number of modules that Quantity restriction per Product Model can be mounted per QCPU system CC-Link IE controller network • QJ71GP21-SX Up to 2 Up to 2 •...
Page 102 CHAPTER2 SYSTEM CONFIGURATION (c) When using the Universal model QCPU Table2.23 Modules of restricted quantity Number of modules that Quantity restriction per Product Model can be mounted per QCPU system CC-Link IE controller network • QJ71GP21-SX • QJ71GP21S-SX module • QJ71LP21 •...
Page 103 (2) Modules that have restrictions on use of a Built-in Ethernet port QCPU Table2.24 lists the module that have restrictions on use of a Built-in Ethernet port QCPU. Table2.24 Modules that have restrictions on use of a Built-in Ethernet port QCPU Five digits of available Product name Model...
Page 104 CHAPTER2 SYSTEM CONFIGURATION (4) Precautions for using QCPU of function version A When the multiple CPU system has been configured using a QCPU of function version A, an error occurs and the multiple CPU system is not started. Errors shown in Table2.25 will occur and the multiple CPU system will not start up if function version A High Performance model QCPUs and High Performance model QCPU/Process CPU are used on a multiple CPU system.
Page 105 (5) Precautions for use of high speed interrupt function íç1 Note2.1 Some system configurations and functions are restricted when the "High speed interrupt fixed scan interval" setting has been mad with a parameter. Qn(H)/QnPH/QnPRH User's Manual (Function Explanation, Program Fundamentals) Note that the above restrictions do not apply to the High Performance model QCPU of serial number "04011"...
Page 106: Mounting Position Of Cpu Module
CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 3.1 Mounting Position of CPU Module For the configuration of the multiple CPU system, the combination of CPU modules shown in Table3.1 is available. Table3.1 Combination of CPU modules Number of CPU that can be mounted on CPU module No.2 or later Maximum Motion CPU...
Page 107: When Cpu No.1 Is Basic Model Qcpu
3.1.1 When CPU No.1 is Basic model QCPU The mounting position of each CPU module is shown in Table3.2. (1) Mounting position of Basic model QCPU Only one Basic model QCPU can be mounted on the CPU slot (slot on the right-hand side of the power supply module) of the main base unit.
Page 108 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM (4) "PLC (Empty)" setting An empty slot can be reserved for future addition of a CPU module. Select the number of CPU modules including empty slots at No. of PLC and set the type of the slots to be emptied to "PLC (Empty)"...
Page 109 (c) When adding the C Controller module in the future. 1) When mounting the Motion CPU Set slot 1 as "PLC (Empty)." Slot number Slot number Added C Controller module Figure 3.5 "PLC (Empty)" setting for addition of C Controller module 2) When not mounting Motion CPU Set slot 0 as "PLC (Empty)."...
Page 110 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM Table3.2 Mounting position of CPU module : Slot number No. of Mounting position of CPU module CPUs ---- ---- *1: No. of CPUs indicates the value set in the multiple CPU setting of the PLC parameter. *2: The PC CPU module occupies 2 slots.
Page 111: When Cpu No.1 Is High Performance Model Qcpu Or Process Cpu
3.1.2 When CPU No.1 is High Performance model QCPU or Process CPU The mounting position of each CPU module is shown in Table3.3. (1) Mounting position of High Performance model QCPU or Process CPU Up to four modules of High Performance model QCPUs or Process CPUs can be mounted from the CPU slot (the slot on the right side of power supply module) to slot 2.
Page 112 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM (5) Mounting position of the C Controller module Up to three C Controller modules can be mounted on slots 0 to 2 of the main base unit. Note that the any CPU module cannot be mounted on the right side of the C Controller module. (6) "PLC (Empty)"...
Page 113 Table3.3 Mounting position of CPU module : Slot number No. of CPUs Mounting position of CPU module ---- *1: The number of CPUs shows the value set by the multiple CPU setting. *2: The PC CPU module occupies two slots. *3: The High Performance model QCPU and Process CPU can be mounted.
Page 114 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM No. of CPUs Mounting position of CPU module *1: The number of CPUs shows the value set by the multiple CPU setting. *2: The PC CPU module occupies two slots. *3: The High Performance model QCPU and Process CPU can be mounted. *4: The High Performance model QCPU, Process CPU, and Universal model QCPU (except Q00UCPU, Q01UCPU, Q02UCPU) can be mounted.
Page 115 No. of CPUs Mounting position of CPU module ---- *1: The number of CPUs shows the value set by the multiple CPU setting. *2: The High Performance model QCPU and Process CPU can be mounted. *3: The High Performance model QCPU, Process CPU, and Universal model QCPU (except Q00UCPU, Q01UCPU, Q02UCPU) can be mounted.
Page 116: When Cpu No.1 Is Universal Model Qcpu
CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 3.1.3 When CPU No.1 is Universal model QCPU The mounting position of each CPU module is shown is Table3.4. (1) Mounting position of Universal model QCPU Only one Q00UCPU, Q01UCPU, Q02UCPU can be mounted on the CPU slot (the right side slot of the power supply module).
Page 117 (6) "PLC (Empty)" setting An empty slot can be reserved for future addition of a CPU module. Select the number of CPU modules including empty slots at No. of PLC and set the type of the slots to be emptied to "PLC (Empty)"...
Page 118 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM Table3.4 Mounting position of CPU module(When the Q00UCPU, Q01UCPU, Q02UCPU is mounted on the CPU No.1) : Slot number No. of CPUs Mounting position of CPU module ---- ---- *1: No. of CPUs indicates the value set in the multiple CPU setting of the PLC parameter. *2: The Q00UCPU, Q01UCPU, Q02UCPU can be mounted.
Page 119 Table3.5 Mounting position of CPU module(When except the Q00UCPU, Q01UCPU, Q02UCPU is mounted on the CPU No.1) : Slot number No. of CPUs Mounting position of CPU module ---- *1: No. of CPUs indicates the value set in the multiple CPU setting of the PLC parameter. *2: Universal model QCPU (except the Q00UCPU, Q01UCPU, Q02UCPU) can be mounted.
Page 120 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM No. of CPUs Mounting position of CPU module ---- *1: No. of CPUs indicates the value set in the multiple CPU setting of the PLC parameter. *2: Universal model QCPU (except the Q00UCPU, Q01UCPU, Q02UCPU) can be mounted. *3: Universal model QCPU (except the Q00UCPU, Q01UCPU, Q02UCPU) and Motion CPU (Q172UDCPU,Q173UDCPU) can be mounted.
Page 121 No. of CPUs Mounting position of CPU module *1: No. of CPUs indicates the value set in the multiple CPU setting of the PLC parameter. *2: Universal model QCPU (except the Q00UCPU, Q01UCPU, Q02UCPU) can be mounted. *3: Universal model QCPU (except the Q00UCPU, Q01UCPU, Q02UCPU) and Motion CPU (Q172UDCPU,Q173UDCPU) can be mounted.
Page 122 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM No. of CPUs Mounting position of CPU module ---- *1: No. of CPUs indicates the value set in the multiple CPU setting of the PLC parameter. *2: Universal model QCPU (except the Q02UCPU) can be mounted. *3: Universal model QCPU (except the Q02UCPU) and Motion CPU (Q172UDCPU,Q173UDCPU) can be mounted.
Page 123: Cpu No. Of Cpu Module
3.2 CPU No. of CPU module (a) CPU No. allocation CPU numbers are allocated for identifying the CPU modules mounted on the main base unit in the multiple CPU system. CPU No.1 is allocated to the CPU slot, and CPU No.2, No.3 and No.4 are allocated to the right of the CPU No.1 in this order.
Page 124 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM • Setting a control CPU in the I/O assignment. Control CPU (Control PLC) setting Figure 3.17 Control CPU setting (b) Checking host CPU number The QCPU stores the host number in the special register (SD395). It is recommended to create a program for checking the host number on the QCPU.
Page 125: Concept Of I/O Number Assignment
3.3 Concept of I/O number assignment In the multiple CPU system, I/O numbers are used for interactive transmission between a CPU module and the I/O modules and intelligent function modules, or between CPU modules. 3.3.1 I/O number assignment of each module The multiple CPU system is different from the Single CPU system in the position (slot) of I/O number 00 However, the concept of the order of allocating I/O numbers, I/O numbers for each slot and empty slots is the same for both types.
Page 126 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM (d) When using the PC CPU module The PC CPU module occupies two slots. The one on the right side among the two slots is handled as an empty slot. (16 empty points are occupied by default.) Therefore the I/O number of the next slot on the right side of the PC CPU module is "10 ."...
Page 127: I/O Number Of Each Cpu Module
3.3.2 I/O number of each CPU module In the multiple CPU system, I/O numbers are assigned to each CPU module to specify mounted CPU modules.íç1 The I/O number for each CPU module is fixed to the corresponding slot and cannot be changed in the I/O assignment of the PLC parameter.
Page 128: Access Range Of Cpu Module And Other Modules
CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 3.4 Access Range of CPU Module and Other Modules 3.4.1 Access range with controlled module In the multiple CPU system a CPU can refresh I/O data of its controlled modules and write or read data of the buffer memory of intelligent function modules in the same way as a single CPU system.
Page 129 (1) Loading input (X) The "I/O sharing when using Multiple CPUs" setting in the PLC parameter's Multiple CPU settings determines whether input can be loaded from input modules and intelligent function modules being controlled by other CPUs. I/O sharing when using Multiple CPUs All CPUs can read all inputs: "All CPUs can read all inputs"...
Page 130 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 2) Input(X) loading is performed for the modules shown in Table3.8, which are mounted to the main base unit or extension base unit(s). Table3.8 Modules that can load inputs I/O allocation type Mounted module Input module High speed input module None...
Page 131 (2) Loading output (Y) The "I/O sharing when using Multiple CPUs" setting in the PLC parameter's Multiple CPU settings determines whether output can be loaded from output modules and intelligent function modules being controlled by other CPUs. I/O sharing when using Multiple CPUs All CPUs can read all outputs: "All CPUs can read all outputs"...
Page 132 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 2) Output(Y) loading is performed for the modules shown in Table3.9, which are mounted to the main base unit or extension base unit(s). Table3.9 Modules that can load outputs I/O allocation type Mounted module Output module None I/O composite module...
Page 133 (3) Output to output modules and intelligent function modules It is not possible to output ON/OFF data to non-controlled modules. Devices will be turned ON or OFF inside the QCPU when the output from output modules or intelligent function modules controlled by other CPUs is turned ON/OFF by a sequence program, but this will not be actually output to the output modules or intelligent function modules.
Page 134 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM (b) Writing to buffer memory The following instructions cannot be used to write data to the buffer memory of intelligent function modules being controlled by other CPUs. • TO instruction • Instructions that use inteligent function module device (U \G ) •...
Page 135: Access Target Under Got Connection
3.5 Access target under GOT connection When a GOT is connected, the access range to QCPU varies depending on the connection method. For details, refer to the GOT manual. 3.6 Access with instruction using link direct device Only control CPUs can execute instructions using link direct devices to access other modules. Link direct devices are not usable for modules being controlled by other CPUs.
Page 136: Access Range Of Gx Developer
CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 3.7 Access range of GX Developer (1) Access to QCPU It is possible to write parameters and programs and perform monitoring and tests on QCPUs connected to GX Developer. To access QCPUs of other CPU No. via a QCPU connected to GX Developer, specify the target CPU No. in the mulple CPU setting of the GX Developer.
Page 137 (2) Access to controlled module and non-controlled module GX Developer can access the modules regardless of whether they are controlled or non-controlled by the QCPU connected to the GX Developr. By connecting GX Developer to a single QCPU, it is possible to perform monitoring and tests on all modules being controlled by the multiple CPU system's QCPU.
Page 138 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM (3) Access from GX Developer in other station From GX Developer connected to other station on the same network, all QCPUs in the multiple CPU system can be accessed. Station No. 2 (normal station) Station No.
Page 139: Clock Data Used By Cpu Module And Intelligent Function Module
3.8 Clock data used by CPU module and intelligent function module This section shows the clock data used by the CPU module and the intelligent function module. 3.8.1 Clock data used by CPU module The following shows the clock data used by the CPU module. (1) Setting of clock data When using the Universal model QCPU, and Motion CPU (Q172DCPU, Q173DCPU) as CPU No.s 2 to 4, the clock data set to the CPU module of CPU No.1 is set to the CPU modules except CPU No.1.
Page 140: Clock Data Used By Intelligent Function Module
CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 3.8.2 Clock data used by intelligent function module Some intelligent function modules store an error code and time (clock data read from QCPU) into the buffer memory when an error occurs. The CPU No.1 time data will be stored as the time for the error regardless of whether the module concerned is a control CPU or a non-control CPU.
Page 141: Resetting The Multiple Cpu System
3.9 Resetting the multiple CPU system The entire multiple CPU system can be reset by resetting CPU No.1. The CPU modules of No.2 to No.4, I/O modules and intelligent function modules will be reset when CPU No.1 is reset. If a stop error occurs in any of the CPUs on the multiple CPU system, either reset CPU No.1 or restart the multiple CPU system (power supply ON ON) for recovery.
Page 142: Operation For Cpu Module Stop Error
CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 3.10 Operation for CPU module stop error The entire system will behaves differently depending whether a stop error occurs in CPU No.1 or any of CPU No.2 to No.4 in the multiple CPU system. (1) When a stop error occurs at CPU No.1 A "MULTI CPU DOWN (error code: 7000)"...
Page 143 If the operation of a CPU is halted by a stop error, a "MULTI CPU DOWN (error code : 7000)" stop error will occur at the CPU on which the error was detected. Depending on the timing of error detection, a "MULTI CPU DOWN" error may be detected in a CPU of "MULTI CPU DOWN" status, not the first CPU on which a stop error occurs.
Page 144 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM (3) System recovery procedure Observe the following procedures to restore the system. 1) Confirm the error-derected CPU No. and error cause with the PLC diagnostics on GX Developer. 2) Remove the error cause. 3) Either reset the CPU No.1 or restart the power to the programmable controller (power ON ON).
Page 145: Host Cpu Number Of Multiple Cpu System
3.11 Host CPU number of multiple CPU system Checking the host CPU number of the multiple CPU system is a function to check whether [Host CPU number] in [Multiple CPU settings] of the PLC parameter is identical to the number of the host CPU which is actually mounted. (The number of the host CPU which is actually mounted is determined by the mounting position of the CPU modules.) Setting the host CPU number Whether host CPU number...
Page 146 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM When making multiple CPU settings of all CPU modules in multiple CPU system same, set "No specification" to "Host CPU number". If [No specification] is set at [Host CPU number], all CPU modules used in the multiple CPU system can share the same multiple CPU setting.
Page 147: Chapter4 Communications Between Cpu Modules
CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES In the multiple CPU system, the following methods are available to read/write data between CPU modules: • Communications with auto refresh ( Section 4.1.2, Section 4.1.3) Data reading/writing between CPU modules • Communications with programs ( Section 4.1.4) Writing/reading of data among the C Controller module, PC CPU module, and QCPU in another CPU Reading the Motion CPU shared memory from the QCPU...
Page 148 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES (1) Communications between CPU modules In the multiple CPU system, various communications between CPU modules are available depending on the communication source and destination CPU module types as shown Table4.1. For communication from the Motion CPU, PC CPU module, and C Controller module, refer to the manuals of each module.
Page 149: Communications Between Cpu Modules Using Cpu Shared Memory
4.1 Communications between CPU modules using CPU shared memory This chapter describes communication methods between CPU modules of the multiple CPU system using the CPU shared memory. First, the CPU shared memory is described. 4.1.1 CPU shared memory The CPU shared memory is a memory provided for each CPU module and by which data are written or read between CPU modules of the multiple CPU system.
Page 150 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES The CPU shared memory configuration and the availability of the communication from the host CPU using the CPU shared memory by program are shown in Figure 4.1 to Figure 4.3. • For Basic model QCPU Host CPU Other CPUs Write...
Page 151 • For Universal model QCPU Host CPU Other CPU CPU shared memory Write Read Write Read Host CPU operation information area ( 1FF G511 ( 200 G512 Restricted system area QCPU standard ( 7FF G2047 area ( 800 G2048 Auto refresh area User setting area ( FFF G4095...
Page 152 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES (1) Host CPU operation information area (a) Information stored in the host CPU operation information area The following information is stored in the host CPU operation infomation area in the multiple CPU system. These will all remain as 0 and will not change in the case of single CPU system. Table4.2 List of host CPU operation information areas Correspo shared...
Page 153 (2) Restricted system area The area used by the system of the CPU module (OS.) (3) Auto refresh area The area used when the multiple CPU system is automatically refreshed. Section 4.1.2) The points from the address next to the last address in the restricted system area are used for auto refresh. (4) User setting area The area for performing communication between CPU modules.
Page 154: Communication By Auto Refresh Using Cpu Shared Memory
CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 4.1.2 Communication by auto refresh using CPU shared memory The following describes communications with auto refresh using auto refresh area in CPU shared memory. For the communication by the auto refresh using the multiple CPU high speed transmission area in the Universal model QCPU , refer to Section 4.1.3.íç1...
Page 155 (1) Communication using auto refresh (a) Operation of auto refresh Auto refresh allows communications using the auto refresh area of the CPU shared memory. By making multiple CPU settings in "PLC parameter", data are automatically written/read between all CPU modules of the multiple CPU system. As device memory data of other CPUs are automatically read by the auto refresh function, the host CPU can use those device data.
Page 156 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES Figure 4.5 shows an outline of operations when CPU No.1 performs auto refresh of 32 points for B0 to B1F, and when CPU No.2 performs auto refresh of 32 points for B20 to B3F. CPU No. 1 CPU No.
Page 157 (2) Refresh settings To perform auto refresh in CPU shared memory, set the number of points to be sent from each CPU module (Send range for each PLC) and a device for storing data (PLC side device) on Multiple CPU settings in PLC parameter.
Page 158 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 3) The number of send points is as follows: • For Basic model QCPU The numbers of send points are 320 words for the Basic model QCPU and 2048 words for the Motion CPU/PC CPU module, making a total of 4416 points (4416 words) for all CPU modules. Basic model QCPU 320 points When the CPU shared Motion CPU 2048 points...
Page 159 4) The area occupied for auto refresh in the CPU shared memory is a total of Setting 1 to 4. When send points are set, the first and last addresses of the auto refresh area are automatically displayed as hexadecimal offset values. For example, the CPU that has send point setting in Setting 1 and 2 has the last address of "the first address of the auto refresh area + offset value of Setting 2".
Page 160 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 5) The same number of send points must be set for all CPUs in the multiple CPU system. If different number of send points is set for a CPU, "PARAMETER ERROR" occurs in the consistency check between CPUs.( Section 6.1(3)) For details of consistency check between CPUs, refer to Section 6.1.
Page 161 3) The CPU devices are set as follows. • It is possible to change the device for settings 1 to 4. The same devices can also be specified as long as the device range for settings 1 to 4 are not overlapped.
Page 162 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES • Devices of setting 1 to 4 can be set independently for each CPU. For example, devices of CPU No.1 can be set up as link relays, and those of CPU No.2 can be set up as internal relays.
Page 163 4) When the auto refresh operations are divided into four ranges (Setting 1: Link relay (B), Setting 2: Link register (W), Setting 3: Data register (D), Setting 4: Internal relay (M)), the outline is as shown in Figure 4.16.íç1 CPU No. 1 Device CPU shared memory Setting 1...
Page 164 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES The followings are available when selecting the method of setting devices with each CPU optionally. • The order of the send range for each module can be changed, since devices can be set individually. • The system scan time can be reduced, since it is possible to set for not performing unnecessary refresh. (Example 1) When changing the order of send range for each CPU module The following shows the example performing auto refresh between High Performance model QCPU of CPU No.1 and Motion CPU of CPU No.2.
Page 165 (Example 2) When setting not to perform unnecessary refresh The following shows the example performing auto refresh between each CPU from No.2 to No.4 and CPU No.1 only. By leaving the device column of other CPUs of which auto refresh is not required in blank, it is possible to set not to perform unnecessary refresh.
Page 166 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES (3) Precautions (a) Local device setting íç1 Note4.6 Device ranges set for the use of the auto refresh cannot be set to local devices. If set, the refresh data will not be updated. (b) Setting for using the same file name as the program in the file register Note4.7 Do not set devices for the use of the auto refresh in the file register for each program.
Page 167 2) Data consistency for data exceeding 32 bits In auto refresh method, data are read in descending order of the setting number in auto refresh setting parameter. Read data separation can be avoided by using the setting number lower than the setting data as an interlock device.
Page 168 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES • Auto refresh between QCPUs Figure 4.22 shows program examples between the High Performance model QCPU when Auto refresh settings in Multiple CPU settings are made as Table4.5. <Parameter setting> Table4.5 Parameter setting example for interlock program CPU shared memory Device at CPU Setting No.
Page 169: Communication By Auto Refresh Using Multiple Cpu High Speed Transmission Area
4.1.3 Communication by auto refresh using multiple CPU high speed transmission area The following describes the communication by the auto refresh using the multiple CPU high speed transmission area in the Universal model QCPU. The communication by the auto refresh using the multiple CPU high speed transmission area can be performed only when the following conditions are all met.
Page 170 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES (1) Communication using auto refresh (a) Overview of auto refresh The auto refresh is a communication method using the auto refresh area of the multiple CPU high speed transmission area in the CPU shared memory. The data written to the auto refresh area of the multiple CPU high speed transmission area is sent to that of the other CPUs in a certain cycle (multiple CPU high speed transmission cycle).
Page 171 (c) Memory configuration of multiple CPU high speed transmission area The following explains the memory configuration of the multiple CPU high speed transmission area of the CPU shared memory that is used in the multiple CPU high speed transmission function. (For the CPU shared memory, refer to Section 4.1.1.) 2) CPU No.1 send range 3) User setting area...
Page 172 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES (2) Multiple CPU high speed transmission area setting To perform auto refresh in CPU shared memory, set the number of points to be sent from each CPU module (Send range for each PLC) and a device for storing data (Auto refresh settings) on Multiple CPU settings in PLC parameter.
Page 173 Selecting "Advanced settings" enables to change the number of points in Restricted system area used for dedicated instructions to 2 k points. Changing the number of points in system area to 2 k enables to increase the number of dedicated instructions can be executed concurrently in a scan.
Page 174 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES (b) Auto refresh setting Auto refresh setting is a setting to use the auto refresh function. The 32 ranges can be set for each CPU modules. Auto refresh setting screen and the setting range are shown below. Figure 4.28 Auto refresh setting screen Table4.9 List of setting item for the refresh setting Item...
Page 175 (3) Auto refresh setting and data flow The following explains the data flow among CPU modules when a multiple CPU system is configured among three CPU modules and auto refresh is set for two ranges. (a) Setting examples of auto refresh to each CPU module Figure 4.29 shows the setting examples of auto refresh to explain the data flow by auto refresh.
Page 176 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES (b) Data flow among CPU modules The following explains the data flow among CPU modules by the auto refresh set as (a). 1) Flow of sending data from CPU No.1 to other CPUs <Parameter setting> Figure 4.30 shows the settings related to sending and receiving CPU No.1 data ((a) to (c) in Figure 4.30) in the setting example of auto refresh in Figure 4.30.
Page 177 2) Flow of sending data from CPU No.2 to other CPUs <Parameter setting> Figure 4.32 shows the settings related to sending and receiving CPU No.2 data ((d) to (f) in Figure 4.32) in the setting example of auto refresh in Figure 4.32. (d) Receive setting from CPU No.2 (e) Send setting of CPU No.2 (f) Receive setting from CPU No.2...
Page 178 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 3) Flow of sending data from CPU No.3 to other CPUs <Parameter setting> Figure 4.34 shows the settings related to sending and receiving CPU No.3 data ((g) to (i) in Figure 4.34) in the setting example of auto refresh in Figure 4.34. (g) Receive setting from CPU No.3 (h) Receive setting of CPU No.3 (i) Send setting from CPU No.3...
Page 179 If Start and End fields in Auto refresh are left blank, auto refresh is not performed. (Start and End fields in Auto refresh in the Receive tab can be left blank.) The example for setting blank to the auto refresh setting .of the CPU No.2 in <Flow of sending data from CPU No.3 to other CPUs>...
Page 180 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES (4) Precautions (a) Local device setting Device ranges set for the use of the auto refresh cannot be set to local devices. If set, the refresh data will not be updated. (b) Setting for using the same file name as the program in the file register Do not set devices for the use of the auto refresh in the file register for each program.
Page 181 Receive side program (CPU No.2) Transmission side program (CPU No.1) (Transmission side (CPU No. 1)) (Reception side (CPU No. 2)) Write command M100 Operation using Set send data receive data from D0 to D9. (D0 to D9) SET M0 SET M32 RST M0 RST M32 1) CPU No.1 stores the send data to D0 to D9.
Page 182: Communication Using Cpu Shared Memory By Program
CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 4.1.4 Communication using CPU shared memory by program This section explains communications with programs using CPU shared memory in a multiple CPU system. Use the following areas in a CPU shared memory for the communications with programs using CPU shared memory. •...
Page 183 (1) Communication made by program (a) Instructions used for writing to/reading from the CPU shared memory The QCPU in a multiple CPU system enables to communicate each CPU module using user free areas in CPU shared memory and multiple CPU high speed transmission area with the write and read instructions.íç1 The Table4.11 shows the write/read instruction.
Page 184 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES (b) Outline of the communication by the program 1) Using user setting area The data written to the CPU shared memory of the host CPU with a write instruction can be read by another CPU using a read instruction. Unlike the auto refresh of the CPU shared memory, it is possible to read up-to-date data directly when this instruction is executed.
Page 185 2) Using user setting aera in multiple CPU high speed transmission area The data written to the multiple CPU high speed transmission area of the CPU shared memory of the host CPU by the write instruction is sent to the other CPU in a certain cycle. The other CPU reads the receive data from the multiple CPU high speed transmission area of the CPU shared memory by the read instruction.
Page 186 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES (c) Memory configuration of multiple CPU high speed transmission area 1) Addresses of user setting area The addresses of user setting area depend on the CPU module. For user setting area addresses, refer to Section 4.1.1. 2) Addresses of multiple CPU high speed transmission area The following explains the memory configuration of the multiple CPU high speed transmission area that is used in the multiple CPU high speed transmission function.
Page 187 (3) Assurance of data sent between CPUs The old data and the new data may be mixed (data separation) in each CPU due to the timing of receiving data from the other CPU and reading in the host CPU. The following shows the method to realize the data consistency of the user data for the data transmission in the multiple CPU high speed transmission function.
Page 188 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES (b) Preventing separation for data exceeding 32 bits 1) Using user setting area Programs are read from the start of user setting area. With the write instruction, send data are written from the last address to the start address of the user setting area.
Page 189 2) Using multiple CPU high speed transmission area In the direct access mode, the data is transferred in order starting from the one which was written to the user setting area first. Using the device which is written after the data transfer regardless of kinds of device or addresses can realize the data consistency of the transferred data.
Page 190 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES (4) Precautions (a) First I/O numbers of CPU modules The following values are set for the CPU module's first I/O number in the write/read instructions. Table4.12 First I/O numbers of CPU modules CPU No. CPU No.1 CPU No.2 CPU No.3 CPU No.4...
Page 191 (e) Data writing to other CPU's shared memory Data cannot be written to the CPU shared memory of other CPU with a write instruction. Writing data to the CPU shared memory of other CPU No. with TO, S.TO instructions or those using the multiple CPU area device (U3En\G ) may result in "SP.
Page 192: Communications Between Cpu Modules When The Error Occurs
CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 4.1.5 Communications between CPU modules when the error occurs (1) Operation when the error occurs to the receive data When the CPU module receives the improper data at the data communication between the CPU modules due to noise or failure, it cancels the receive data.
Page 193: Communications With Instructions Dedicated To Motion Cpu
4.2 Communications with instructions dedicated to Motion CPU 4.2.1 Control instruction from QCPU to Motion CPU Control instructions can be issued from the QCPU to Motion CPU with the instructions dedicated to Motion CPU as listed in Table4.14. (Control instructions from a Motion CPU to other Motion CPU is not allowed.) Table4.14 List of instructions dedicated to Motion CPU CPU module Universal model QCPU...
Page 194 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES (Example) When using the S.SFCS instruction It is possible to start up the Motion CPU's motion SFC from the QCPU. Motion CPU QCPU Motion SFC Start request S.SFCS instruction Figure 4.45 Operation of S.SFCS instruction One QCPU can concurrently issue up to 32 instructions of "Instructions dedicated to Motion CPU"...
Page 195: Communication With Dedicated Instructions
4.3 Communication with Dedicated Instructions 4.3.1 Writing/reading of device data from QCPU to Motion CPU The QCPU can write/read device data to/from the Motion CPU with the multiple CPU transmission dedicated instruction and multiple CPU high-speed transmission dedicated instruction. (Writing/reading from the Motion CPU to other CPU modules including the Motion CPU is not allowed.) (Example) Using the S.DDWR instruction The QCPU device data can be written to the Motion CPU devices.
Page 196 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES (2) Multiple CPU high-speed transmission dedicated instruction The Universal model QCPU can write/read device data to/from the Q172DCPU and Q173DCPU with the multiple CPU high-speed transmission dedicated instruction shown on Table4.16. Table4.16 List of multiple CPU high-speed transmission dedicated instructions CPU module Universal model QCPU Q03UD(E)CPU...
Page 197 4.3.2 Starting interrupt program from QCPU to C Controller module/PC CPU module Using the multiple CPU transmission dedicated instruction in Table4.17, an interrupt program can be started from the QCPU to the C Controller module/PC CPU module. The interrupt program from the PC CPU module to other CPU module cannot be started. An interrupt program can be started from the C Controller module to the Motion CPU or the C Controller module in another CPU.
Page 198: Writing/Reading Of Device Data From Qcpu To Qcpu
CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 4.3.3 Writing/reading of device data from QCPU to QCPU The Universal model QCPU can write/read device data to/from another Universal model QCPU with the multiple CPU high-speed transmission dedicated instruction shown on Table4.18. Table4.18 List of multiple CPU high-speed transmission dedicated instructions CPU module Universal model QCPU Q03UD(E)CPU...
Page 199: Multiple Cpu Synchronous Interrupt
4.4 Multiple CPU Synchronous Interrupt The multiple CPU synchronous interrupt function executes interrupt programs (multiple CPU synchronous interrupt programs) at the timing of multiple CPU high speed transmission cycle. The multiple CPU synchronous interrupt enables synchronization with multiple CPU high speed transmission cycle and communications among CPU modules.
Page 200 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES When a multiple CPU synchronous interrupt factor occurs during the execution of another interrupt program, the running program is aborted to execute the multiple CPU synchronous interrupt program. Interrupt request from I45 Interrupt request from In Sequence program IRET Interrrupt program...
Page 201: Multiple Cpu Synchronized Boot-Up
4.5 Multiple CPU Synchronized Boot-up Multiple CPU synchronized boot-up function synchronizes the start-ups of CPU No.1 to CPU No.4. Since this function monitors the startup of each CPU module, when another station is accessed by manual operation, an interlock program which checks the CPU module startup is unnecessary. With the multiple CPU synchronized boot-up function, the start-up is synchronized with the CPU module of slow start- up;...
Page 202 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES The Multiple CPU synchronous startup setting cannot be made for the CPU modules except the Universal model QCPU (except the Q00UCPU, Q01UCPU, Q02UCPU) and Motion CPU (Q172DCPU, Q173DCPU). When these modules have been used, deselect the relevant CPUs at the Multiple CPU synchronous startup setting. For example, when using the High Performance model QCPU to CPU No.2 and No.4, deselect No.2 and No.4.
Page 203: Chapter5 Processing Time Of Qcpu In Multiple Cpu System 5-1 To
CHAPTER5 PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM 5.1 Concept of Scan Time The concept of scan time in the multiple CPU system is the same as that in the single CPU system. This chapter describes how to calculate the processing time when the multiple CPU system is configured. (1) I/O refresh time I/O refresh time is calculated with the equation explained in the following manual.
Page 204 CHAPTER5 PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM (3) Common processing The values in Table5.2 show the common processing time. Table5.2 END processing time QCPU Common processing time Q00CPU (0.05 to 0.13) (No. of other CPUs)ms Q01CPU Q02CPU 0.02ms Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU 0.03ms...
Page 205: Factors For Prolonged Scan Time
5.2 Factors for prolonged Scan Time The processing time in Multiple CPU Systems is prolonged in comparison with Single CPU Systems when the following functions are used. When using the following, add the values described later to the values calculated in Section 5.1. •...
Page 206 CHAPTER5 PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM (b) Calculation of auto refresh time The automatic refresh time of the CPU shared memory is calculated in the following equation. 1) For Basic model QCPU (Auto refresh time) = (N1 + (No. of transmission word points) N2)) + (N3 + (No.
Page 207 3) For Universal model QCPU (Auto refresh time) = (N1 + (No. of transmission word points) N2)) + (N3 + (No. of other CPUs) N4 + (No. of reception word points) N5) (µs) • The number of received words is the sum of the numbers of words transmitted by the other CPUs. (Example) When No.
Page 208 CHAPTER5 PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM (c) When auto refresh of another CPU occurs during auto refresh processing of a CPU If auto refresh of another CPU occurs during auto refresh processing of a CPU, the auto refresh time increases by the time obtained from each the following calculations.
Page 209 (2) Refresh of CC-Link IE controller network MELSECNET/Híç1 Note5.2 (a) Refresh time of CC-Link IE controller network and MELSECNET/H The amount of time required for performing the refresh between the QCPU and the CC-Link IE controller network or MELSECNET/H network module. For refresh time of CC-Link IE controller network and MELSECNET/H, refer to the following manual.
Page 210 CHAPTER5 PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM 2) For High Performance model QCPU /Process CPU /Universal Note5.3 Note5.4 model QCPUíç1 (Extension time) = (No. of transmission/reception word points) (No. of other CPUs) ( s) The number of transmission/reception words is the total number of transfer data below.
Page 211 (3) CC-Link auto refresh (a) Auto refresh time on CC-Link network The amount of time required for performing the refresh process between QCPU and CC-Link master local modules. Refer to the following manual for details on the auto refresh time for CC-Link. QJ61BT11N CC-Link System Master Local Module User's Manual (b) Calculation of auto refresh time The amount of time required for the auto refresh process will be prolonged only by the following amount of time...
Page 212: Reducing Processing Time
CHAPTER5 PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM 5.3 Reducing processing time (1) Multiple CPU system processing Access is made between a CPU module and an I/O module or intelligent function module through a bus (base unit pattern, extension cable) and this bus cannot be used by multiple CPU modules at the same time. If more than one CPU module attempt to use it simultaneously, the CPU module attempted access later is placed in "Standby"...
Page 213: Chapter6 Parameter Added For Multiple Cpu System
CHAPTER6 PARAMETER ADDED FOR MULTIPLE CPU SYSTEM 6.1 Parameter list (1) Parameters that enable the use of multiple CPU system Comparing with a single CPU system, a multiple CPU system has additional settings of "Multiple CPU settings" in PLC parameter and "Control PLC" setting in I/O assignment setting. The same PLC parameter must be set to all the CPU modules used in the multiple CPU system, except some settings.
Page 214 CHAPTER6 PARAMETER ADDED FOR MULTIPLE CPU SYSTEM Table6.1 Setting list for the multiple CPU and I/O Assignment íç1 Necessity Necessity of same PLC parameter Reference of setup setting I/O Assignment Type ---- Model name ---- ---- Points ---- StartXY ---- Base setting Qn(H)/QnPH/QnPRH Base model name...
Page 215 (b) For Universal model QCPU The Table6.2 shows the PLC parameter settings that are required when the Universal model QCPU is used. Table6.2 Setting list for the multiple CPU and I/O Assignment Necessity Necessity of same PLC parameter Reference of setup setting I/O Assignment Type...
Page 216 CHAPTER6 PARAMETER ADDED FOR MULTIPLE CPU SYSTEM Necessity Necessity of same PLC parameter Reference of setup setting No. of PLC Section 6.1.1 Host CPU number Operation mode Section 6.1.2 Multiple CPU synchronized boot-up Section 6.1.7 Online module change Section 6.1.3 All CPUs can read all inputs Section 6.1.4 All CPUs can read all outputs...
Page 217 (3) Multiple CPU parameters check At the time of the multiple CPU system power-on, reset or mode change from STOP to RUN of CPU No.1, or parameter change, whether the multiple CPU parameters are the same settings for all CPUs or not is checked as shown in Table6.3 with items marked in the Necessity of same setting column in Table6.1 and 6.2 (Consistency check between CPU modules).
Page 218: Number Of Cpus Setting
CHAPTER6 PARAMETER ADDED FOR MULTIPLE CPU SYSTEM 6.1.1 Number of CPUs setting (1) No. of PLC The number of CPU modules to be used on a multiple CPU system are set at the PLC parameter's "Multiple CPU settings" screen in the PLC parameter dialog box. Figure 6.1 No.
Page 219 (2) Reserving empty slot When an empty slot is reserved for the purpose of mounting additional CPU modules in the future, set "PLC (Empty)" on the "I/O assignment" tab screen in the "PLC parameter" dialog box. For example, when setting "4" as "No. of CPUs" in use of High Performace model QCPU and reserving one of them for future use, set "CPU (Empty)"...
Page 220: Operating Mode Setting
CHAPTER6 PARAMETER ADDED FOR MULTIPLE CPU SYSTEM 6.1.2 Operating mode setting This is set to continue operation of other CPUs where a stopping error has not occurred when an error occurs at other than CPU No.1.íç1 The operating mode for the CPU No.1 cannot be changed (all CPUs will suspend operations when a stop error is triggered for the CPU No.1.) Section 3.10 6.1.3 Online module change setting...
Page 221: Control Cpu Settings
6.1.6 Control CPU settings Sets up the control CPUs (Control PLCs) for the I/O modules and intelligent function modules mounted on the base unit in the multiple CPU system. All default settings are set to CPU No.1. Figure 6.3 Control CPU setting screen 6.1.7 Multiple CPU synchronized boot-up This is set for synchronizing the boot-up time for each CPU module.
Page 222: Chapter7 Precautions For Using Ans/A Series-Compatible Modules
CHAPTER7 PRECAUTIONS FOR USING AnS/A SERIES-COMPATIBLE MODULES CHAPTER7 PRECAUTIONS FOR USING ANS/A SERIES- COMPATIBLE MODULES 7.1 Precautions for use of AnS/A series compatible module (1) Multiple CPU configuration available for AnS/A series compatible modules AnS/A series compatible modules can be used for the multiple CPU configuration satisfied with the following all conditions.
Page 223 (Example) When the control CPU is setup for CPU No.2 Set CPU No.2 to the control CPU for all slots where the AnS/A series-compatible modules are mounted. If setting different CPU as the control CPU among any one of the AnS/A series-compatible module, "PARAMETER ERROR"...
Page 224 CHAPTER7 PRECAUTIONS FOR USING AnS/A SERIES-COMPATIBLE MODULES (3) Ranges of access to controlled and non-controlled modules Table7.1 indicates access range to the controlled and non-controlled modules in the multiple CPU system. Table7.1 Access range to controlled module and non-controlled module Non-controlled module (I/O setting outside of the group) Controlled...
Page 225 (b) Unavailable modules The modules shown in Table7.3 cannot be used. Table7.3 List of unavailable modules Module Name Type A1SJ71LP21,A1SJ71BR11,A1SJ71QLP21, A1SJ71QLP21S,A1SJ71QLP21GE,A1SJ71QBR11, MELSECNET/10 network module AJ71LP21,AJ71LP21G,AJ71BR11,AJ71LR21, AJ71QLP21,AJ71QLP21S,AJ71QLP21G, AJ71QBR11,AJ71QLR21 A1SJ71AP21,A1SJ71AR21,A1SJ71AT21B, MELSECNET (II), /B data link module AJ71AP21,AJ71AP21-S3,AJ71AR21,AJ71AT21B A1SJ71QE71-B2-S3(-B5-S3), Ethernet interface module A1SJ71E71-B2-S3(-B5-S3) AJ71QE71N(-B5T),AJ71E71-B2(-B5T) Serial communication module or computer link A1SJ71QC24(N),A1SJ71UC24-R2(-PRF),...
Page 226: Chapter8 Starting Up The Multiple Cpu System
CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM This Chapter explains the standard start-up procedures for the multiple CPU system.íç1 8.1 Flow-chart for Starting Up the Multiple CPU System Parameters should be preset and sequence programs should be prepared in advance. ( Section 8.2, Section 8.3) For parameter setting and program creation of the Motion CPU, C Controller module, and PC CPU module, refer to the manuals of each CPU module.
Page 227 (From previous page) Writing parameter and Manual of the Motion CPU program to the Motion CPU Writing parameter and program Manual of the C Controller module to the C Controller module Writing parameter and Manual of the PC CPU module program to the PC CPU module RUN/STOP switch setting for all CPUs Set RUN/STOP switch *...
Page 228: Setting Up The Multiple Cpu System Parameters
CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM 8.2 Setting Up the Multiple CPU System Parameters This section explains the procedures for setting multiple CPU parameter with GX Developer. Refer to the GX Developer's operation manual for details on setting up all other parameters. 8.2.1 Parameter setting for the Basic model QCPU,High Paformance model QCPU,Process CPU (1) System configuration...
Page 229 (2) Parameters required for multiple CPU system When the multiple CPU system is used, the following parameter settings are required.íç1 Parameters of "Same setting items for each CPU module" should be set with the same settings in all CPU modules used in the multiple CPU system except some parts.( Section 6.1) No.
Page 230 CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM (3) When creating a new multiple CPU system Start The operating manual of GX Developer. Start-up of GX Developer Open the PLC parameter setting window The operating manual of GX Developer. for parameters of GX Developer. Select "PLC system"...
Page 231 íç1 (From previous page) Select "Multiple CPU settings" and display the multiple CPU setting window. No. of PLC (mandatory item) Set the number of CPU modules mounted on the main base unit with the multiple CPU Note8.3 system. (To next page) Basic Note8.3 Since the number of CPU modules that can be mounted is up to 3 when using the basic model QCPU, do not set to...
Page 232 CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM íç1 (From previous page) Operating mode (option) Select if all CPUs are stopped/operated for occurrence of stop error. Default: With any error of CPUs 2, 3 and 4, all CPUs stop (checked). For example, when "All station stop by stop error of PLC 2"...
Page 233 (From previous page) Refresh settings (option) With change of settings, 4 settings from setting 1 to setting can be made. After setting, select "Setting completed" and close the multiple CPU setting window. Select "I/O assignment" and display the I/O assignment setting window. I/O assignment (option) Select the slot to "PLC (Empty)"...
Page 234 CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM íç1 (From previous page) Control PLC (mandatory item) Select control PLC (PLC No. 1 to PLC No. 4) Note8.5 for each slot. For the intelligent function module of function version A, set Control PLC to PLC No. 1. For the AnS/A series-compatible module, set Control PLC to all same High Performance Note8.6...
Page 235 (4) Reusing preset multiple CPU parameters Start Start-up of GX Developer Refer to the operating manual of GX Developer. Open the PLC parameter setting window for the parameter of GX Developer. Select "Multiple CPU settings" and display the multiple CPU setting window. Carry-over of multiple CPU setting Click "Import Multiple CPU Parameter".
Page 236 CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Setting of carry-over project Select the project that carries over multiple CPU setting and I/O assignment. Click "Open". When "OK" is selected, the multiple CPU setting and the I/O assignment setting data are read from the specified project and the data is overwritten.
Page 237 (From previous page) Select "PLC system" and display the PLC system setting window. Check the empty slot points on the PLC system setting window. (To next page) 8 - 12...
Page 238 CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Select "I/O assignment" and display the I/O assignment setting window. Check the I/O assignment settings and basic settings in the I/O assignment setting window. Select "Detailed setting" and display the detail setting window.
Page 239 (From previous page) Check settings of the control CPU. Set parameters for non-multiple CPU system. Write set parameters in the hard disk/floppy disk. Completed Figure 8.5 Parameter setting procedure for reusing multiple CPU system parameters 8 - 14...
Page 240: Parameter Setting For The Universal Model Qcpu
CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM 8.2.2 Parameter setting for the Universal model QCPU (1) System configuration Figure 8.2 shows an example procedures for setting up the multiple CPU parameters. PC (GX Developer) Empty slot for addition of future CPU module Slot number CPU 0 Control CPU...
Page 241 (2) Parameters required for multiple CPU system When the multiple CPU system is used, the following parameter settings are required. Parameters of "Same setting items for each CPU module" should be set with the same settings in all CPU modules used in the multiple CPU system except some parts.( Section 6.1) Multiple CPU setting No.
Page 242 CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM (3) When creating a new multiple CPU system Start The operating manual of GX Developer. Start-up of GX Developer Open the PLC parameter setting window The operating manual of GX Developer. for parameters of GX Developer. Select "PLC system"...
Page 243 (From previous page) Select "Multiple CPU settings" and display the multiple CPU setting window. The number of mountable CPU modules depends on the CPU model. Q00UCPU, Q01UCPU, Q02UCPU: PLC No.1 to PLC No.3 Except the Q00UCPU, Q01UCPU, Q02UCPU: PLC No.1 to PLC No.4 No.
Page 244 CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Operating mode (option) Select if all CPUs are stopped/operated for occurrence of stop error. Default: With any error of CPUs 2, 3 and 4, all CPUs stop (checked). For example, when "All station stop by stop error of PLC 2"...
Page 245 (From previous page) The number of points setting in Send range for each Set the number of points to be sent/received among CPU modules. Set them within the following number of points. No. of PLC Setting range 0 to 14k points 0 to 13k points 0 to 12k points Set 0 point for the following CPU modules:...
Page 246 CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Select "I/O assignment" and display the I/O assignment setting window. I/O assignment (option) Select the slot to "PLC (Empty)" that does not mount the CPU module for each type. Select the type of each module from the pulldown menu.
Page 247 (From previous page) Control PLC (mandatory item) Select Control PLC for each slot. Selectable numbers depend on the CPU module used. Q00UCPU,Q01UCPU,Q02UCPU: PLC No.1 to PLC No.3 Except the Q00UCPU,Q01UCPU,Q02UCPU: PLC No.1 to PLC No.4 Set parameters for non-multiple CPU system. Write set parameters in the hard disk/floppy disk.
Page 248: Reusing Preset Multiple Cpu Parameters
CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM 8.2.3 Reusing preset multiple CPU parameters Start Start-up of GX Developer Refer to the operating manual of GX Developer. Open the PLC parameter setting window for the parameter of GX Developer. Select "Multiple CPU settings" and display the multiple CPU setting window.
Page 249 (From previous page) Setting of carry-over project Select the project that carries over multiple CPU setting and I/O assignment. Click "Open". When "OK" is selected, the multiple CPU setting and the I/O assignment setting data are read from the specified project and the data is overwritten. Check the multiple CPU settings.
Page 250 CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Select "PLC system" and display the PLC system setting window. Check the empty slot points on the PLC system setting window. (To next page) 8 - 25...
Page 251 (From previous page) Select "I/O assignment" and display the I/O assignment setting window. Check the I/O assignment settings and basic settings in the I/O assignment setting window. Select "Detailed setting" and display the detail setting window. (To next page) 8 - 26...
Page 252 CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM (From previous page) Check settings of the control CPU. Set parameters for non-multiple CPU system. Write set parameters in the hard disk/floppy disk. Completed Figure 8.9 Parameter setting procedure for reusing multiple CPU system parameters 8 - 27...
Page 253: Communication Program Examples Using Auto Refresh
8.3 Communication program examples using auto refresh 8.3.1 Program examples for the Basic model QCPU, High Performance model QCPU and Process CPU This section explains program examples in the following system configuration given in Figure 8.10 and assignment of the data communications between CPU modules. PC (GX Developer) CPU 0 Slot number...
Page 254 CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM Figure 8.12 Auto refresh area settings 8 - 29...
Page 255 (2) Example of bit & word data transmission from CPU No. 1 to No. 2 Table8.1 Auto refresh devices used in each CPU module Auto refresh devices used in CPU No. 1 Auto refresh devices used in CPU No. 2 D0,D1 D0,D1 Program example...
Page 256 CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM (3) Example of continuous data transmission from CPU No. 1 to No. 2 Table8.2 Auto refresh devices used in each module Auto refresh devices used in CPU No. 1 Auto refresh devices used in CPU No. 2 D10 to D18 D10 to D18 For handshake in CPU Nos.
Page 257 (4) Writing/reading using the user setting area of the CPU shared memory by a program (a) Memory addresses for auto refresh setting to user setting area The same points must be set for CPU No.1 and CPU No.2 in the auto refresh setting. Figure 8.15 Auto refresh setting (same settings) The auto refresh area occupies the area from setting 1 and setting 2 to memory address of 0800 to 0821...
Page 258 CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM (b) Program example of continuous data writing/reading using the user setting area from CPU No. 2 to CPU No. 1 Table8.3 Auto refresh devices used in each CPU module Auto refresh device used in CPU No. 2 Auto refresh device used in CPU No.
Page 259: Program Examples For The Universal Model Qcpu
8.3.2 Program examples for the Universal model QCPU This section explains program examples in the following system configuration given in Figure 8.18 and assignment of the data communications between CPU modules. PC (GX Developer) CPU 0 Slot number A/D D/A Input Input Output...
Page 260 CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM Figure 8.20 Auto refresh area setting 8 - 35...
Page 261 (2) Example of bit & word data transmission from CPU No. 1 to No. 2 Table8.4 Auto refresh devices used in each CPU module Auto refresh devices used in CPU No. 1 Auto refresh devices used in CPU No. 2 D0,D1 D0,D1 Program example...
Page 262 CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM (3) Example of continuous data transmission from CPU No. 1 to No. 2 Table8.5 Auto refresh devices used in each module Auto refresh devices used in CPU No. 1 Auto refresh devices used in CPU No. 2 D10 to D18 D10 to D18 For handshake in CPU Nos.
Page 263 (4) Writing/reading using the user setting area of the CPU shared memory by a program (a) Memory addresses for auto refresh setting to user setting area In the auto refresh setting, make same settings for CPU No. 1 and CPU No. 2. Figure 8.23 Auto refresh setting (same settings) User free area will be from 3E0\G10000 for CPU No.1 and from 3E1\G10000 for CPU No.2.
Page 264 CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM (5) Program example of continuous data writing/reading using the user setting area from CPU No. 2 to CPU No. 1 Table8.6 Auto refresh devices used in each CPU module Auto refresh device used in CPU No. 2 Auto refresh device used in CPU No.
Page 265 INDEX A5 B ....... . . A-21 GOT ........A-22 B.
Page 266 Continuous data writing/reading using the user setting area ....8-33,8-39 Sending bit and word data ... . 8-30,8-36 PX Developer .
Page 267 WARRANTY Please confirm the following product warranty details before using this product. 1. Gratis Warranty Term and Gratis Warranty Range If any faults or defects (hereinafter "Failure") found to be the responsibility of Mitsubishi occurs during use of the product within the gratis warranty term, the product shall be repaired at no cost via the sales representative or Mitsubishi Service Company.
Page 270 Phone: +370 (0)5 / 232 3101 Fax: +370 (0)5 / 232 2980 MITSUBISHI ELECTRIC Mitsubishi Electric Europe B.V. /// FA - European Business Group /// Gothaer Straße 8 /// D-40880 Ratingen /// Germany Tel.: +49(0)2102-4860 /// Fax: +49(0)2102-4861120 /// info@mitsubishi-automation.com /// www.mitsubishi-automation.com FACTORY AUTOMATION...

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Mitsubishi Electric MELSEC Q Series User Manual

Chapter 1 Outline

Chapter 2 System Configuration

Chapter 3 Concept for Multiple Cpu System

Chapter4 Communications Between Cpu Modules

CHAPTER5 PROCESSING TIME of QCPU in MULTIPLE CPU SYSTEM 5-1 to

Chapter6 Parameter Added for Multiple Cpu System

CHAPTER7 PRECAUTIONS FOR USING Ans/A SERIES-COMPATIBLE MODULES

Chapter8 Starting Up the Multiple Cpu System

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