Intel ® Quickpath Interconnect (Intel ® Qpi) Specifications; Intel Quickpath Interconnect (Intel Qpi) Specifications - Intel BX80613I7980 Datasheet

®
2.12 Intel
Specifications
The processor Intel QPI specifications in this section are defined at the processor pins.
Routing topologies are dependent on the processors supported and the chipset used in
the design. In most cases, termination resistors are not required as these are
integrated into the processor silicon.
®
Table 2-17. Intel QuickPath Interconnect (Intel QPI) Specifications
Symbol
Average UI size at "x" GT/s
UIavg
(Where x= 4.8 GT/s, 6.4 GT/s, etc.)
Defined as the slope of the rising or
falling waveform as measured between
T
slew-rise-fall-pin
±100 mV of the differential transmitter
output, for any data or clock.
Defined as:
± (max(Z
Z min(Z
TX_LOW_CM_DC TX_LOW_CM_DC
expressed in%, over full range of Tx
single ended voltage
Defined as: ±(max(Z
min(Z
TX_LOW_CM_DC
Z
RX_LOW_CM_DC
expressed in%, over full range of Tx
single ended voltage
# of UI over which the eye mask voltage
N and timing specification needs to be
MIN-UI-Validation
validated
Single ended DC impedance to GND for
Z
TX_HIGH_CM_DC
either D+ or D- of any data bit at Tx
Single ended DC impedance to GND for
Z
RX_HIGH_CM_DC
either D+ or D- of any data bit at Tx
Link Detection Resistor
Z
TX_LINK_DETECT
Phase variability between reference Clk
T
Refclk-Tx-Variability
(at Tx input) and Tx output.
Phase skew between D+ and D- lines for
L
D+/D-RX-Skew
any data bit at Rx
Time taken by clock detector to observe
T
CLK_DET
clock stability
Time taken by clock frequency detector
T to decide slow vs operational clock after
CLK_FREQ_DET
stable clock
Bit Error Rate per lane valid for 4.8 GT/s
BER
Lane
and 6.4 GT/s
% error in Tx equalization setting as
TX measured by errors in DC levels when
EQ-error
sending a steady "1".
QPI_CMP[0] COMP Resistance
Notes:
1. Indicates the output impedance of the transmitter during initialization when the transmitter is "OFF", that is, the output driver
is disconnected and only the minimum termination is connected. The link detection resistor is assumed not connected when
specifying this parameter.
2. Used during initialization. It is the state of "OFF" condition for the receiver when only the minimum termination is connected.
3. COMP resistance must be provided on the system board with 1% resistors. QPI_CMP[0] resistors are to V
32
QuickPath Interconnect (Intel
Parameter
) –
TX_LOW_CM_DC
)) /Z
TX_LOW_CM_DC
) –
TX_LOW_CM_DC
)) /Z
TX_LOW_CM_DC
Min Nom Max
0.999 * 1.001 *
1000/f
nominal nominal
10 25
—
-6 0
-6 0
1,000,000
—
10 k
—
10 k
—
500 2000
—
500
— —
0.03
— —
20K
— —
32
— —
1.0E-14
— —
-10 0 10
20.79 21 21.21
Electrical Specifications
®
QPI)
Unit Notes
psec
V / nsec
% of
6
Z
TX_LOW_CM_DC
% of
6
Z
TX_LOW_CM_DC
—

—

—

psec
UI
UI
Reference
Clock Cycles
Events
% of V
O

SS.
Datasheet, Volume 1
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