Table of Contents
Advertisement
2.11.1
DC Voltage and Current Specification
Table 2-7.
Voltage and Current Specifications
Symbol
VID
V
CC
V
TTA
V
TTD
V
DDQ
V
CCPLL
I
CC
I
TTA
I
TTD
I
DDQ
I
S3
DDQ
I
CC_VCCPLL
Notes:
1.
Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical
data. These specifications will be updated with characterized data from silicon measurements at a later date
2.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note that
this differs from the VID employed by the processor during a power management event (Adaptive Thermal
Monitor, Enhanced Intel SpeedStep
3.
The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the
socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 M minimum
impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external
noise from the system is not coupled into the oscilloscope probe.
4.
Refer to
processor should not be subjected to any V
5.
See
Table 2-9
Loadline
6.
I
CC_MAX
7.
This specification is based on a processor temperature, as reported by the DTS, of less than or equal to
T
CONTROL
24
Parameter
VID range
Processor
V
for processor core
CC
Number
i7-990X
3.46 GHz
i7-980X
3.33 GHz
i7-980
3.33 GHz
i7-970
3.20 GHz
Voltage for the analog portion of the
integrated memory controller, QPI link
and Shared Cache
Voltage for the digital portion of the
integrated memory controller, QPI link
and Shared Cache
Processor I/O supply voltage for DDR3
PLL supply voltage (DC + AC
specification)
Processor
I
for processor
CC
Number
i7-990X
3.46 GHz
i7-980X
3.33 GHz
i7-980
3.33 GHz
i7-970
3.20 GHz
Current for the analog portion of the
integrated memory controller, QPI link
and Shared Cache
Current for the digital portion of the
integrated memory controller, QPI link
and Shared Cache
Processor I/O supply current for DDR3
Processor I/O supply current for DDR3
while in S3
PLL supply current (DC + AC specification)
®
Table 2-8
Figure 2-3
and
for the minimum, typical, and maximum V
for details on V
Voltage Identification. See
TT
specification is based on the V
CC_MAX
–25.
Min
0.8
See
Table 2-8
See
Table 2-10
See
Table 2-9
1.425
1.71
—
—
—
—
—
—
Technology, or Low Power States).
and I
combination wherein V
CC
CC
Table 2-10
Figure 2-3
loadline. Refer to
Electrical Specifications
Typ
Max
Unit
Notes
1.375
V
and
Figure 2-3
V
and
Figure 2-4
V
and
Figure 2-4
V
1.5
1.575
V
1.8
1.89
V
145
—
A
145
145
145
—
5
A
—
23
A
—
6
A
—
1
A
—
1.1
A
allowed for a given current. The
CC
exceeds V
for a given current.
CC
CC_MAX
and
Figure 2-4
for details on the V
for details.
Datasheet, Volume 1
1
2
3,4
5
5
6
7
TT
Hide quick links:
Advertisement
Table of Contents
