Mchbar Register Details; C0Drb0-Channel A Dram Rank Boundary Address 0 - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

MCHBAR Registers
Address
Offset
195–19Fh
1A0–1A3h
1A4–F0Fh
F10–F13h
F14h
5.1

MCHBAR Register Details

5.1.1 C0DRB0—Channel A DRAM Rank Boundary Address 0
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
The DRAM Rank Boundary Register defines the upper boundary address of each DRAM rank
with a granularity of 32 MB. Each rank has its own single-byte DRB register. These registers are
used to determine which chip select will be active for a given address.
Channel and Rank Map:
Channel A Rank 0:
Channel A Rank 1:
Channel A Rank 2:
Channel A Rank 3:
Channel B Rank 0:
Channel B Rank 1:
Channel B Rank 2:
Channel B Rank 3:
Single Channel or Asymmetric Channels Example
If the channels are independent, addresses in Channel B should begin where addresses in Channel
A left off, and the address of the first rank of Channel A can be calculated from the technology
(256 Mbit, 512 Mbit, or 1 Gbit) and the x8 or x16 configuration. With independent channels, a
value of 01h in C0DRB0 indicates that 32 MB of DRAM has been populated in the first rank, and
the top address in that rank is 32 MB.
80
Register
Symbol
— Reserved
C1DRC0 Channel B DRAM Controller Mode 0
— Reserved
PMCFG Power Management Configuration
PMSTS Power Management Status
MCHBAR
100h
00h
R/W
8 bits
100h
101h
102h
103h
180h
181h
182h
183h
Register Name
®
Intel 82925X/82925XE MCH Datasheet
R
Default
Access
Value
— —
00000000h R/W, RO
— —
00000000h R/W
00000000h R/W/C/S