Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Specification
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Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Specification

Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Specification

Specification update
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®
®
Δ
Intel
Pentium
D Processor 900
®
®
Sequence and Intel
Pentium
Processor Extreme Edition 955,
Δ
965
Specification Update
- On 65 nm Process in the 775-land LGA Package
®
supporting Intel® 64 Architecture and Intel
Virtualization
±
Technology
May 2008
Document Number:
310307-018

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Summary of Contents for Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU

  • Page 1 D Processor 900 ® ® Sequence and Intel Pentium Processor Extreme Edition 955, Δ Specification Update - On 65 nm Process in the 775-land LGA Package ® supporting Intel® 64 Architecture and Intel Virtualization ± Technology May 2008 Document Number: 310307-018...
  • Page 2 Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. ®...

  • Page 3: Table Of Contents

    Contents Contents ..........................3 Revision History ........................4 Preface ..........................5 Summary Tables of Changes ....................7 General Information......................13 Identification Information ....................14 Errata ..........................16 Specification Changes ......................32 Specification Clarifications ....................33 Documentation Changes ......................34 Specification Update...

  • Page 4: Revision History

    Description Date -001 • Initial release December 2005 -002 • Added Intel Pentium D processor 900 sequence specifications January 2006 -003 • Updated related documents, added processor number February 2006 -004 • Replaced AA5 with new erratum, added erratum AA31 March 2006 ®...

  • Page 5: Preface

    Processor Extreme Edition 955 , 965 Datasheet Related Documents Document Title Document Number Intel® 64 and IA-32 Architectures Software Developer's http://www.intel.com/products/ Manual Volume 1: Basic Architecture, document 253665 processor/manuals/index.htm Intel® 64 and IA-32 Architectures Software Developer's http://www.intel.com/products/ Manual Volume 2A: Instruction Set Reference Manual A–...
  • Page 6 Preface Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number QDF Number is a several digit code that is used to distinguish between engineering samples.

  • Page 7: Summary Tables Of Changes

    The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
  • Page 8 Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) Mobile Intel® Pentium® 4 processor-M 64-bit Intel®...
  • Page 9 Intel® Core™ 2 Duo processor E8000 series AX = Quad-Core Intel® Xeon® processor 5400 series Dual-Core Intel® Xeon® processor 5200 series Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on AZ = 45-nm Process AAA = Quad-Core Intel® Xeon® processor 3300 series AAB = Dual-Core Intel®...
  • Page 10 Access to an Unsupported Address Range in Uniprocessor (UP) ® AA14 No Fix or Dual-processor (DP) Systems Supporting Intel Virtualization Technology May Not Trigger Appropriate Actions VM Exit Due to a MOV from CR8 May Cause an Unexpected AA15 Fixed...
  • Page 11 An Unexpected Memory Access May be Issued During AA43 No Fix Execution of the WRMSR Instruction Under Certain Conditions Plan Combining Some Processors With Intel 945® Chipsets Can AA44 Lead to Unpredictable System Behavior A VM Exit Occuring in IA-32e Mode May Not Produce a VMX AA45...
  • Page 12 Summary Tables of Changes Number Plan SPECIFICATION CLARIFICATIONS There are no Specification Clarification in this Specification Update revision Number Plan DOCUMENTATION CHANGES There are no Documentation Changes in this Specification Update revision. § Specification Update...

  • Page 13: General Information

    General Information General Information ® ® Figure 1. Intel Pentium D Processor 900 Sequence (Package Top Markings) ® ® Figure 2. Intel Pentium Processor Extreme Edition 965 (Package Top Markings) § Specification Update...

  • Page 14: Identification Information

    Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register. Refer to the Intel Processor Identification and the CPUID Instruction Application Note (AP-485). ®...
  • Page 15 ® 3. These parts support Enhanced Intel SpeedStep Technology and Enhanced HALT State. 4. These parts support Hyper-Threading Technology. ® 5. These parts do NOT support Enhanced Intel SpeedStep Technology or Enhanced HALT State 6. These parts support Intel ®...

  • Page 16: Errata

    Implication: If this erratum occurs in an HT Technology enabled system, the application may temporarily stop making forward progress. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 17 Errata AA3. Data Breakpoints on the High Half of a Floating Point Line Split May Not Be Captured When a floating point load which splits a 64-byte cache line gets a floating Problem: point stack fault, and a data breakpoint register maps to the high line of the floating point load, internal boundary conditions exist that may prevent the data breakpoint from being captured.
  • Page 18 General Protection Fault (#GP) if the FDP or FP Instruction Pointer (FIP) is in non-canonical form. Implication: When this erratum occurs, Intel EM64T enabled systems may encounter an unintended #GP fault. Workaround: Software should avoid using non-canonical effective addressing in EM64T enabled processors.
  • Page 19 Workaround: Define BTS/PEBS buffer such that BTS/PEBS absolute maximum minus BTS/PEBS buffer base is integer multiple of the corresponding record sizes as ® recommended in the IA-32 Intel Architecture Software Developer’s Manual, Volume 3. For the steppings affected, see the Summary Tables of Changes.
  • Page 20 FFFFFFFFh, the 64-bit value of LIP in the PEBS record will be incorrect (upper 32 bits will be set to FFFFFFFFh when they should be 0). Implication: Intel has not observed this erratum on any commercially available software. Workaround: None identified.
  • Page 21 Errata AA14. Access to an Unsupported Address Range in Uniprocessor (UP) or ® Dual-processor (DP) Systems Supporting Intel Virtualization Technology May Not Trigger Appropriate Actions ® When using processors supporting Intel Virtualization Technology and Problem: configured as dual- or single-processor-capable (i.e. not multiprocessor- capable), the processor should perform address checks using a maximum physical address width of 36.
  • Page 22 Implication: When this erratum occurs, the processor may livelock and result in a system hang. Intel has only observed this erratum while injecting cache errors in simulation.. Workaround: None identified.
  • Page 23 Wait-For-SIPI or Shutdown states Implication: Due to this erratum, Interrupt-Window-Exiting VM exits may take the logical processor out of Wait-For-SIPI and Shutdown states. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for the BIOS to contain a workaround for this erratum For the steppings affected, see the Summary Tables of Changes.
  • Page 24 Errata AA23. Machine Check Exceptions May not Update Last-Exception Record MSRs (LERs) The Last-Exception Record MSRs (LERs) may not get updated when Machine Problem: Check Exceptions occur Implication: When this erratum occurs, the LER may not contain information relating to the machine check exception.
  • Page 25 Status: AA27. The Execution of a VMPTRLD Instruction May Cause an Unexpected Memory Access ® In a system supporting Intel Virtualization Technology, executing VMPTRLD Problem: may cause a memory access to an address not referenced by the memory operand. Implication: This erratum may cause unpredictable system behavior including system hang.
  • Page 26 •L2 Data Write Errors (IA32_MC1_STATUS with MCA error code 145) Implication: Uncorrected or corrected L2 ECC machine check errors may be erroneously reported. Intel has not observed this erratum on any commercially available system. Workaround: When a real run-time L2 Cache ECC Machine Check occurs, a corresponding valid error will normally be logged in the IA32_MC0_STATUS register.
  • Page 27 Exposure to this problem requires the use of a data write which spans a cache line boundary. Implication: This erratum may cause loads to be observed out of order. Intel has not observed this erratum with any commercially available software or system.
  • Page 28 Loaded from a Far Jump through a Call Gate via the Local Descriptor Table In IA-32e mode of the Intel EM64T processor, control transfers through a call Problem: gate via the Local Descriptor Table (LDT) that uses a 16-byte descriptor, the upper 8-byte access may wrap and access an incorrect descriptor in the LDT.
  • Page 29 AA40. NMI-blocking Information Recorded in VMCS May be Incorrect after a #GP on an IRET Instruction ® In a system supporting Intel Virtualization Technology, the NMI blocking bit Problem: in the Interruption-Information Field in the guest VMCS may be set incorrectly.
  • Page 30 Unpredictable System Behavior Some processors with 800 MHz Front Side Bus (FSB), when used in Problem: combination with a motherboard based on the Intel 945® chipset, may observe FSB bit errors which may result in unpredictable system behavior. Specification Update...
  • Page 31 Errata Implication: Due to this erratum, FSB marginality is observed during processor core to core transactions as well as during read transactions driven by the Memory Controller Hub (MCH) leading to unpredictable system behavior. Workaround: It is possible for BIOS to contain a workaround for this erratum. For the steppings affected, see the Summary Tables of Changes.

  • Page 32: Specification Changes

    Pentium D processor 900 sequence and Pentium processor Extreme Edition 955, 965 documentation. Δ Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature.

  • Page 33: Specification Clarifications

    ® ® ® • Intel Pentium D Processor 900 Sequence and Intel Pentium Processor Extreme Edition 955, 965 Datasheet All Specification Clarifications will be incorporated into a future version of the appropriate Pentium D processor 900 sequence and Pentium processor Extreme Edition 955, 965 documentation.

  • Page 34: Documentation Changes

    Note: Documentation changes for Intel 64 and IA-32 Architecture Software Developer’s ® Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document Intel 64 and IA-32 Architecture Software Developer’s Manual Documentation Changes. Follow the link below to become familiar with this file.

This manual is also suitable for:

Pentum d 900 sequencePentium extreme edition 955Pentium extreme edition 965

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