Ma-Message Address (D1:F0); Md-Message Data (D1:F0) - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

R
8.1.29 MA—Message Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Bit
31:2
1:0
8.1.30 MD—Message Data (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Bit
15:0
®
Intel 82925X/82925XE MCH Datasheet
Access &
Default
R/W Message Address: This field is used by system software to assign an MSI
00000000 h address to the device.
The device handles an MSI by writing the padded contents of the MD register to
this address.
RO Force DWord Align: Hardwired to 0 so that addresses assigned by system
00b software are always aligned on a DWord address boundary.
Access &
Default
R/W Message Data: This field provides a base message data pattern assigned by
0000h system software and used to handle an MSI from the device.
When the device must generate an interrupt request, it writes a 32-bit value to
the memory address specified in the MA register. The upper 16 bits are always
set to 0. This register supplies the lower 16 bits.
Host-PCI Express* Graphics Bridge Registers (D1:F0)
1
94h
00000000h
RO, R/W
32 bits
Description
1
98h
0000h
R/W
16 bits
Description
133