Pga370 Socket Definition Details; Platform Pin Definition Comparison For Single Processor Designs - Intel 810A3 Design Manual

PGA370 Processor Design Guidelines
2.2

PGA370 Socket Definition Details

The following tables compare legacy pin names and functions to new flexible pin names and
functions. Designers need to pay close attention to the notes section for this table for compatibility
concerns regarding these pin changes.
Table 2-1. Platform Pin Definition Comparison for Single Processor Designs
Pin #
A29
A31
A33
AC1
AC37
AF4
AH20
AH4
AJ31
AK16
AK24
AL11
AL13
AL21
AM2
AN11
AN13
AN15
AN23
B36
C29
C31
C33
E29
E31
G35
V4
W3
X4
X6
Y33
2-2
Legacy Flexible
PGA370 PGA370
pin name pin name
Reserved DEP7#
Reserved DEP3#
Reserved DEP2#
Reserved A33#
Reserved RSP#
Reserved A35#
Reserved VTT
Reserved RESET#
GND BSEL1
Reserved VTT
Reserved AERR#
Reserved AP0#
Reserved VTT
Reserved VTT
GND Reserved
Reserved VTT
Reserved AP1#
Reserved VTT
Reserved RP#
Reserved BINIT#
Reserved DEP5#
Reserved DEP1#
Reserved DEP0#
Reserved DEP6#
Reserved DEP4#
Reserved VTT
Reserved BERR#
Reserved A34#
RESET# RESET2#
Reserved A32#
GND CLKREF
Function
Data bus ECC data
Data bus ECC data
Data bus ECC data
Additional AGTL+ address
Response parity
Additional AGTL+ address
AGTL+ termination voltage
®
Processor reset (Intel
®
Pentium III)
System bus frequency select
AGTL+ termination voltage
Address parity error
Address parity
AGTL+ termination voltage
AGTL+ termination voltage
Reserved
AGTL+ termination voltage
Address parity
AGTL+ termination voltage
Request parity
Bus initialization
Data bus ECC data
Data bus ECC data
Data bus ECC data
Data bus ECC data
Data bus ECC data
AGTL+ termination voltage
Bus error
Additional AGTL+ address
Processor reset (Value
processors)
Additional AGTL+ address
1.25V PLL reference
®
Intel
Type Notes
AGTL+, I/O 2
AGTL+, I/O 2
AGTL+, I/O 2
AGTL+, I/O 2
AGTL+, I 2
AGTL+, I/O 2
Power
AGTL+, I 3
CMOS, I/O 1
Power
AGTL+, I/O 2
AGTL+, I/O 2
Power
Power
Reserved 1
Power
AGTL+, I/O 2
Power
AGTL+, I/O
AGTL+, I/O 2
AGTL+, I/O 2
AGTL+, I/O 2
AGTL+, I/O 2
AGTL+, I/O 2
AGTL+, I/O 2
Power
AGTL+, I/O 2
AGTL+, I/O 2
AGTL+, I 3
AGTL+, I/O 2
Power 1
810A3 Chipset Design Guide