Eple2D-Ep Link Entry 2 Description - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

EPBAR Registers—Egress Port Register Summary
6.1.4 EPLE2D—EP Link Entry 2 Description
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
This register provides the First part of a Link Entry that declares an internal link to another Root
Complex Element.
Bit
31:24
23:16
15:2
1
0
96
Access &
Default
RO Target Port Number: This field specifies the port number associated with the
02h element targeted by this link entry (PCI Express* x16 Graphics Interface). The
target port number is with respect to the component that contains this element as
specified by the target component ID.
R/WO Target Component ID: This field identifies the physical or logical component that
00h is targeted by this link entry. A value of 0 is reserved; Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
Reserved
RO Link Type:
1b
1 = Link points to configuration space of the integrated device that controls the
x16 root port. The link address specifies the configuration address (segment,
bus, device, function) of the target root port.
R/WO Link Valid
0b
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
EPBAR
060h
02000002h
R/WO, RO
32 bits
Description
®
Intel 82925X/82925XE MCH Datasheet
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