Nintendo 1504166 - Game Boy Advance SP Edition Console Programming Manual page 158

AGB Programming Manual
3) Interrupt Request Register
When an interrupt request signal is generated from each hardware device, the
corresponding interrupt request flag is set in the IF Register.
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Address Register
202h IF
If a 1 is written to the bit which the interrupt request flag is set in, that interrupt request
flag can be reset
[Cautions regarding clearing IME and IE]
A corresponding interrupt could occur even while a command to clear IME or each flag
of the IE register is being executed.
When clearing a flag of IE, you need to clear IME in advance so that mismatching of
interrupt checks will not occur.
When multiple interrupts are used
When the timing of clearing of IME and the timing of an interrupt agree, multiple
interrupts will not occur during that interrupt. Therefore, set (enable) IME after saving
IME during the interrupt routine.
©1999 - 2001 Nintendo of America Inc.
DMA DMA DMA DMA Timer Timer
3 2 1 0 3
Serial Communication/General Purpose
Communication/UART Communication
DMA
Key
Game Pak(DREQ/IREQ)
158
Attributes Initial Value
Timer Timer
H V
2 1 0
Rendering Blank
V Counter Matching
Timer
Communication/JOY Bus
D.C.N. AGB-06-0001-002B4
Interrupt Control
R 0000h