Table 26. Bios Setup Ide Configuration Menu Options - Intel SE7525RP2 Technical Manual

Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS
BIOS
Feature
Adjacent Cache Line
Prefetch
Hyper-Threading Technology
HT Technology in MPS
Intel SpeedStep®
Technology
6.4.5.2.2 IDE Configuration Sub-menu
Feature
IDE Configuration
Onboard PATA Disabled
Channels
Primary
Secondary
Both
Onboard SATA Disabled
Channels
Enabled
Configure SATA as
Disabled
RAID
Enabled
SATA Ports Definition
A1-3
A1-4
Revision 1.0
Options
This option enables / disables
Disabled
the processor Adjacent Cache
Enabled
Line Prefetch Feature.
Changing the default may
affect performance depending
on the application being used.
Disabled Enable Hyper-Threading
Technology only if operating
Enabled
system supports it.
Enabling adds secondary
Disabled
processor threads to the MPS
Enabled
Table for pre-ACPI OSes.
Only enable this feature if the
pre-ACPI operating system
supports Hyper-Threading
Technology.
Auto Select disabled for maximum
CPU speed. Select Auto to
Disabled
allow the operating system to
reduce power consumption.

Table 26. BIOS Setup IDE Configuration Menu Options

Options
Disabled: disables the
integrated PATA Controller.
Primary: enables only the
Primary PATA Controller.
Secondary: enables only the
Secondary PATA Controller.
Both: enables both PATA
Controllers.
Disabled: disables the
integrated SATA Controller.
Enabled: enables the
integrated SATA Controller.
When enabled the SATA
channels are reserved to be
used as RAID.
rd th Defines priority between SATA
M/A2-4 M
channels.
th rd
M/A2-3 M
Intel order number D24635-001
Help Text
Controls Hyper-Threading state.
Primarily used to support older
Operating Systems that do not
support Hyper Threading.
Note: This feature is hidden if
the processor does not support
it.
Help Text
Controls state of integrated PATA
controller.
Controls state of integrated SATA
controller.
Default set the SATA Port0 to
third IDE Master channel and
Port1 to fourth IDE Master
channel.
Otherwise set SATA Port0 to
fourth IDE Master channel and
Port1 to third IDE Master channel.
Description
Description
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