Network Interface Controller (Nic); Nic Connector And Status Leds; Interrupt Routing; Legacy Interrupt Routing - Intel SE7525RP2 Technical Manual

Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS
PCI I/O Subsystem
5.3

Network Interface Controller (NIC)

The server boards SE7320EP2 and SE7525RP2 support one 10Base-T / 100Base / 1000Base-
T network interface controller (NIC) based on the Intel® 82541PI controller (NIC 2) and one
gigabit network interface controller based on the Marvell* 88E8050 controller (NIC 1).
The Intel 82541PI Gigabit Ethernet is a single, compact component with an integrated Gigabit
Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For desktop,
workstation and mobile PC network designs with critical space constraints, the Intel 82541PI
allows for a Gigabit Ethernet implementation in a very small area that is footprint compatible
with current generation 10/100 Mbps Fast Ethernet designs. The Intel 82541PI integrates fourth
generation gigabit MAC design with fully integrated, physical layer circuitry to provide a standard
IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE_TX, and 10BASE-T applications
(802.3, 802.3u, and 802.3ab). The controller is capable of transmitting and receiving data at
rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition to managing MAC and PHY layer
functions, the controller provides a 32-bit wide direct Peripheral Component Interconnect (PCI)
2.3 compliant interface capable of operating at 33 or 66MHz.
The single-chip PCI Express based 88E8050 device integrates the Marvell Gigabit PHY with the
Marvell Gigabit MAC and SERDES cores, delivering an ultra-small form factor and high
performance. The 88E8050 device is compliant with the PCI Express 1.0a specification. Offered
in a 9 x 9 mm, 64-pin QFN package, the 88E8050 reduces board space required for Gigabit
LOM implementation.
5.3.1

NIC Connector and Status LEDs

The NICs drive two LEDs located on each network interface connector. For each NIC
connector, the green LED indicates network connection when on, and Transmit/Receive activity
when blinking. The yellow LED indicates 1000-Mbps operation when lit, the green LED indicates
100-Mbps operation when lit and 10-Mbps when off.
5.4

Interrupt Routing

The board interrupt architecture accommodates both PC-compatible PIC mode and APIC mode
interrupts through use of the integrated I/O APICs in the 6300ESB ICH.
5.4.1

Legacy Interrupt Routing

For PC-compatible mode, the 6300ESB ICH provides two 82C59-compatible interrupt
controllers. The two controllers are cascaded with interrupt levels 8-15 entering on level 2 of the
primary interrupt controller (standard PC configuration). A single interrupt signal is presented to
the processors, to which only one processor will respond for servicing. The 6300ESB ICH
contains configuration registers that define which interrupt source logically maps to I/O APIC
INTx pins.
The 6300ESB ICH handles both PCI and IRQ interrupts. The 6300ESB ICH translates these to
the APIC bus. The numbers in the table below indicate the 6300ESB ICH PCI interrupt input pin
to which the associated device interrupt (INTA, INTB, INTC, INTD, INTE, INTF, INTG, INTH for
PCI bus and PXIRQ0, PXIRQ1, PXIRQ2, PXIRQ3 for PCI-X bus) is connected. The 6300ESB
ICH I/O APIC exists on the I/O APIC bus with the processors.
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Intel order number D24635-001
Revision 1.0