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Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ66.
LER MSRs May Be Unreliable
Problem:
Due to certain internal processor events, updates to the LER (Last Exception Record)
MSRs, MSR_LER_FROM_LIP (1DDH) and MSR_LER_TO_LIP (1DEH), may happen when
no update was expected.
Implication: The values of the LER MSRs may be unreliable.
Workaround:None Identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ67.
MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance
of a DTLB Error
Problem:
A single Data Translation Look Aside Buffer (DTLB) error can incorrectly set the
Overflow (bit [62]) in the MCi_Status register. A DTLB error is indicated by MCA error
code (bits [15:0]) appearing as binary value, 000x 0000 0001 0100, in the MCi_Status
register.
Implication: Due to this erratum, the Overflow bit in the MCi_Status register may not be an accurate
indication of multiple occurrences of DTLB errors. There is no other impact to normal
processor functionality.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ68.
Debug Exception Flags DR6.B0-B3 Flags May Be Incorrect for Disabled
Breakpoints
Problem:
When a debug exception is signaled on a load that crosses cache lines with data
forwarded from a store and whose corresponding breakpoint enable flags are disabled
(DR7.G0-G3 and DR7.L0-L3), the DR6.B0-B3 flags may be incorrect.
Implication: The debug exception DR6.B0-B3 flags may be incorrect for the load if the
corresponding breakpoint enable flag in DR7 is disabled.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ69.
This Erratum is Removed as it Does not Apply to the Intel Celeron
P4000 and U3000 Mobile Processor Series
Problem:
N/A
Implication: N/A
Workaround:N/A
Status:
N/A
AAZ70.
Delivery of Certain Events Immediately Following a VM Exit May Push
a Corrupted RIP onto the Stack
Problem:
If any of the following events is delivered immediately following a VM exit to 64-bit
mode from outside 64-bit mode, bits 63:32 of the RIP value pushed on the stack may
be cleared to 0:
• A non-maskable interrupt (NMI);
• A machine-check exception (#MC);
• A page fault (#PF) during instruction fetch; or
• A general-protection exception (#GP) due to an attempt to decode an instruction
whose length is greater than 15 bytes.
34
Errata
Specification Update
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