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Errata
AAZ39.
Sleeping Cores May Not Be Woken up on Logical Cluster Mode
Broadcast IPI Using Destination Field Instead of Shorthand
Problem:
If software sends a logical cluster broadcast IPI using a destination shorthand of 00B
(No Shorthand) and writes the cluster portion of the Destination Field of the Interrupt
Command Register to all ones while not using all 1s in the mask portion of the
Destination Field, target cores in a sleep state that are identified by the mask portion of
the Destination Field may not be woken up. This erratum does not occur if the
destination shorthand is set to 10B (All Including Self) or 11B (All Excluding Self).
Implication: When this erratum occurs, cores which are in a sleep state may not wake up to handle
the broadcast IPI. Intel has not observed this erratum with any commercially-available
software.
Workaround:Use destination shorthand of 10B or 11B to send broadcast IPIs.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ40.
Faulting Executions of FXRSTOR May Update State Inconsistently
Problem:
The state updated by a faulting FXRSTOR instruction may vary from one execution to
another.
Implication: Software that relies on x87 state or SSE state following a faulting execution of
FXRSTOR may behave inconsistently.
Workaround:Software handling a fault on an execution of FXRSTOR can compensate for execution
variability by correcting the cause of the fault and executing FXRSTOR again.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ41.
Performance Monitor Event EPT.EPDPE_MISS May Be Counted While
EPT Is Disabled
Problem:
Performance monitor event EPT.EPDPE_MISS (Event: 4FH, Umask: 08H) is used to
count Page Directory Pointer table misses while EPT (extended page tables) is enabled.
Due to this erratum, the processor will count Page Directory Pointer table misses
regardless of whether EPT is enabled or not.
Implication: Due to this erratum, performance monitor event EPT.EPDPE_MISS may report counts
higher than expected.
Workaround:Software should ensure this event is only enabled while in EPT mode.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ42.
Memory Aliasing of Code Pages May Cause Unpredictable System
Behavior
Problem:
The type of memory aliasing contributing to this erratum is the case where two
different logical processors have the same code page mapped with two different
memory types. Specifically, if one code page is mapped by one logical processor as
write-back and by another as uncachable and certain instruction fetch timing conditions
occur, the system may experience unpredictable behavior.
Implication: If this erratum occurs the system may have unpredictable behavior including a system
hang. The aliasing of memory regions, a condition necessary for this erratum to occur,
is documented as being unsupported in the Intel 64 and IA-32 Intel
Software Developer's Manual, Volume 3A, in the section titled Programming the PAT.
Intel has not observed this erratum with any commercially-available software or
system.
Workaround:Code pages should not be mapped with uncacheable and cacheable memory types at
the same time.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
®
Architecture
27
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