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Errata
AAZ54.
VM Exits Due to EPT Violations Do Not Record Information about Pre-
IRET NMI Blocking
Problem:
With certain settings of the VM-execution controls VM exits due to EPT violations set bit
12 of the exit qualification if the EPT violation was a result of an execution of the IRET
instruction that commenced with non-maskable interrupts (NMIs) blocked. Due to this
erratum, such VM exits will instead clear this bit.
Implication: Due to this erratum, a virtual-machine monitor that relies on the proper setting of bit
12 of the exit qualification may deliver NMIs to guest software prematurely.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ55.
Multiple Performance Monitor Interrupts Are Possible on Overflow of
IA32_FIXED_CTR2
Problem:
When multiple performance counters are set to generate interrupts on an overflow and
more than one counter overflows at the same time, only one interrupt should be
generated. However, if one of the counters set to generate an interrupt on overflow is
the IA32_FIXED_CTR2 (MSR 30BH) counter, multiple interrupts may be generated
when the IA32_FIXED_CTR2 overflows at the same time as any of the other
performance counters.
Implication: Multiple counter overflow interrupts may be unexpectedly generated.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ56.
LBRs May Not Be Initialized during Power-On Reset of the Processor
Problem:
If a second reset is initiated during the power-on processor reset cycle, the LBRs (Last
Branch Records) may not be properly initialized.
Implication: Due to this erratum, debug software may not be able to rely on the LBRs out of power-
on reset.
Workaround:Ensure that the processor has completed its power-on reset cycle prior to initiating a
second reset.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ57.
LBR, BTM or BTS Records May Have Incorrect Branch from
Information after an Enhanced Intel SpeedStep® Technology
Transition, T-states, C1E, or Adaptive Thermal Throttling
Problem:
The "From" address associated with the LBR (Last Branch Record), BTM (Branch Trace
Message) or BTS (Branch Trace Store) may be incorrect for the first branch after an
Enhanced Intel SpeedStep Technology transition, T-states, C1E (C1 Enhanced), or
Adaptive Thermal Throttling.
Implication: When the LBRs, BTM or BTS are enabled, some records may have incorrect branch
"From" addresses for the first branch after an Enhanced Intel SpeedStep Technology
transition, T-states, C1E, or Adaptive Thermal Throttling.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ58.
VMX-Preemption Timer Does Not Count Down at the Rate Specified
Problem:
The VMX-preemption timer should count down by 1 every time a specific bit in the TSC
(Time Stamp Counter) changes. (This specific bit is indicated by IA32_VMX_MISC bits
[4:0] (0x485h) and has a value of 5 on the affected processors.) Due to this erratum,
the VMX-preemption timer may instead count down at a different rate and may do so
only intermittently.
Specification Update
31
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