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Workaround:Software should never write to the address range armed by the MONITOR instruction
between the MONITOR and the subsequent MWAIT.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ19.
Performance Monitor Event SEGMENT_REG_LOADS Counts
Inaccurately
Problem:
The performance monitor event SEGMENT_REG_LOADS (Event 06H) counts
instructions that load new values into segment registers. The value of the count may be
inaccurate.
Implication: The performance monitor event SEGMENT_REG_LOADS may reflect a count higher or
lower than the actual number of events.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ20.
#GP on Segment Selector Descriptor That Straddles Canonical
Boundary May Not Provide Correct Exception Error Code
Problem:
During a #GP (General Protection Exception), the processor pushes an error code on to
the exception handler's stack. If the segment selector descriptor straddles the
canonical boundary, the error code pushed onto the stack may be incorrect.
Implication: An incorrect error code may be pushed onto the stack. Intel has not observed this
erratum with any commercially-available software.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ21.
Improper Parity Error Signaled in the IQ Following Reset When a Code
Breakpoint Is Set on a #GP Instruction
Problem:
While coming out of cold reset or exiting from C6, if the processor encounters an
instruction longer than 15 bytes (which causes a #GP) and a code breakpoint is
enabled on that instruction, an IQ (Instruction Queue) parity error may be incorrectly
logged resulting in an MCE (Machine Check Exception).
Implication: When this erratum occurs, an MCE may be incorrectly signaled.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ22.
An Enabled Debug Breakpoint or Single Step Trap May Be Taken after
MOV SS/POP SS Instruction If It Is Followed by an Instruction That
Signals a Floating Point Exception
Problem:
A MOV SS/POP SS instruction should inhibit all interrupts including debug breakpoints
until after execution of the following instruction. This is intended to allow the sequential
execution of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without having an
invalid stack during interrupt handling. However, an enabled debug breakpoint or single
step trap may be taken after MOV SS/POP SS if this instruction is followed by an
instruction that signals a floating point exception rather than a MOV [r/e]SP, [r/e]BP
instruction. This results in a debug exception being signaled on an unexpected
instruction boundary since the MOV SS/POP SS and the following instruction should be
executed atomically.
Implication: This can result in incorrect signaling of a debug exception and possibly a mismatched
Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]SP,
[r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any
exception. Intel has not observed this erratum with any commercially-available
software or system.
22
Errata
Specification Update
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