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Errata
Implication: This erratum can affect software only if a far RET instruction is executed after a VM
entry that erroneously clears the B bit and only if the following other three conditions
are also true: (1) the SS register is not loaded between VM entry and far RET; (2) the
far RET instruction is executed in 64-bit mode with an immediate operand; (3) the far
RET instruction makes a transition to compatibility mode without changing CPL
(Current Privilege Level). Due to the far RET being executed with an immediate
operand, an adjustment is made to the stack pointer. Normally, when SS is unusable
the SS.B bit is 1 and the adjustment will be to the 32-bit ESP register. Due to this
erratum, the adjustment will incorrectly be made to the 16-bit SP register. Intel has not
observed this erratum with any commercially available software.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ96.
Accesses to a VMCS May Not Operate Correctly If CR0.CD is Set on Any
Logical Processor of a Core
Problem:
The VMX (virtual-machine extensions) are controlled by the VMCS (virtual-machine
control structure). If CR0.CD is set on any logical processor of a core, operations using
the VMCS may not function correctly. Such operations include the VMREAD and
VMWRITE instructions as well as VM entries and VM exits.
Implication: If CR0.CD is set on either logical processor in a core, the VMWRITE instruction may not
correctly update the VMCS and the VMREAD instruction may not return correct data.
VM entries may not load state properly and may not establish VMX controls properly.
VM exits may not save or load state properly.
Workaround:VMMs (Virtual-machine monitors) should ensure that CR0.CD is clear on all logical
processors of a core before entering VMX operation on any logical processor. Software
should not set CR0.CD on a logical processor if any logical processor of the same core is
in VMX operation. VMM software should prevent guest software from setting CR0.CD by
setting bit 30 in the CR0 guest/host mask field in every VMCS.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ97.
Performance Monitor Events for Hardware Prefetches Which Miss The
L1 Data Cache May be Over Counted
Problem:
Hardware prefetches that miss the L1 data cache but cannot be processed immediately
due to resource conflicts will count and then retry. This may lead to incorrectly
incrementing the L1D_PREFETCH.MISS (event 4EH, umask 02H) event multiple times
for a single miss.
Implication: The count reported by the L1D_PREFETCH.MISS event may be higher than expected.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ98.
Correctable and Uncorrectable Cache Errors May be Reported Until the
First Core C6 Transition
Problem:
On a subset of processors it is possible that correctable/uncorrectable cache errors may
be logged and/or a machine check exception may occur prior to the first core C6
transition. The errors will be logged in IA32_MC5_STATUS MSR (415H) with the
MCACOD (Machine Check Architecture Error Code) bits [15:0] indicating a Cache
Hierarchy Error of the form 000F 0001 RRRR TTLL.
Implication: Due to this erratum, correctable/uncorrectable cache error may be logged or signaled.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
41
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