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Errata
Workaround:As recommended in the IA32 Intel
of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP will avoid the failure since
the MOV [r/e]SP, [r/e]BP will not generate a floating point exception. Developers of
debug tools should be aware of the potential incorrect debug event signaling created by
this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ23.
IA32_MPERF Counter Stops Counting during On-Demand TM1
Problem:
According to the Intel
Volume 3A: System Programming Guide, the ratio of IA32_MPERF (MSR E7H) to
IA32_APERF (MSR E8H) should reflect actual performance while Intel TM1 or on-
demand throttling is activated. Due to this erratum, IA32_MPERF MSR stops counting
while Intel TM1 or on-demand throttling is activated, and the ratio of the two will
indicate higher processor performance than actual.
Implication: The incorrect ratio of IA32_APERF/IA32_MPERF can mislead software P-state
(performance state) management algorithms under the conditions described above. It
is possible for the Operating System to observe higher processor utilization than actual,
which could lead the OS into raising the P-state. During Intel TM1 activation, the OS P-
state request is irrelevant and while on-demand throttling is enabled, it is expected
that the OS will not be changing the P-state. This erratum should result in no practical
implication to software.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ24.
The Memory Controller tTHROT_OPREF Timings May Be Violated
during Self-Refresh Entry
Problem:
During self-refresh entry, the memory controller may issue more refreshes than
permitted by tTHROT_OPREF (bits 29:19 in MC_CHANNEL_{0,1}_REFRESH_TIMING
CSR).
Implication: The intention of tTHROT_OPREF is to limit current. Since current supply conditions near
self refresh entry are not critical, there is no measurable impact due to this erratum.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ25.
Synchronous Reset of IA32_APERF/IA32_MPERF Counters on
Overflow Does Not Work
Problem:
When either the IA32_MPERF or IA32_APERF MSR (E7H, E8H) increments to its
maximum value of 0xFFFF_FFFF_FFFF_FFFF, both MSRs are supposed to synchronously
reset to 0x0 on the next clock. This synchronous reset does not work. Instead, both
MSRs increment and overflow independently.
Implication: Software can not rely on synchronous reset of the IA32_APERF/IA32_MPERF registers.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ26.
Disabling Thermal Monitor While Processor Is Hot, Then Re-enabling,
May Result in Stuck Core Operating Ratio
Problem:
If a processor is at its TCC (Thermal Control Circuit) activation temperature and then
Thermal Monitor is disabled by a write to IA32_MISC_ENABLES MSR (1A0H) bit [3], a
subsequent re-enable of Thermal Monitor will result in an artificial ceiling on the
maximum core P-state. The ceiling is based on the core frequency at the time of
Thermal Monitor disable. This condition will only correct itself once the processor
reaches its TCC activation temperature again.
Specification Update
®
Architecture Software Developer's Manual, the use
®
64 and IA-32 Architectures Software Developer's Manual
23
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