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Errata
AAZ15.
MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in
Hang
Problem:
If the target linear address range for a MONITOR or CLFLUSH is mapped to the local
xAPIC's address space, the processor will hang.
Implication: When this erratum occurs, the processor will hang. The local xAPIC's address space
must be uncached. The MONITOR instruction only functions correctly if the specified
linear address range is of the type write-back. CLFLUSH flushes data from the cache.
Intel has not observed this erratum with any commercially-available software.
Workaround:Do not execute MONITOR or CLFLUSH instructions on the local xAPIC address space.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ16.
Corruption of CS Segment Register during RSM While Transitioning
from Real Mode to Protected Mode
Problem:
During the transition from real mode to protected mode, if an SMI (System
Management Interrupt) occurs between the MOV to CR0 that sets PE (Protection
Enable, bit 0) and the first FAR JMP, the subsequent RSM (Resume from System
Management Mode) may cause the lower two bits of CS segment register to be
corrupted.
Implication: The corruption of the bottom two bits of the CS segment register will have no impact
unless software explicitly examines the CS segment register between enabling
protected mode and the first FAR JMP. Intel
Developer's Manual Volume 3A: System Programming Guide, Part 1, in the section
titled "Switching to Protected Mode" recommends the FAR JMP immediately follows the
write to CR0 to enable protected mode. Intel has not observed this erratum with any
commercially-available software.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ17.
Performance Monitoring Events for Read Miss to Level 3 Cache Fill
Occupancy Counter May Be Incorrect
Problem:
Whenever an Level 3 cache fill conflicts with another request's address, the miss to fill
occupancy counter, UNC_GQ_ALLOC.RT_LLC_MISS (Event 02H), will provide erroneous
results.
Implication: The Performance Monitoring UNC_GQ_ALLOC.RT_LLC_MISS event may count a value
higher than expected. The extent to which the value is higher than expected is
determined by the frequency of the L3 address conflict.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ18.
A VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware
As Armed
Problem:
A processor write to the address range armed by the MONITOR instruction may not
immediately trigger the monitoring hardware. Consequently, a VM exit on a later
MWAIT may incorrectly report the monitoring hardware as armed, when it should be
reported as unarmed due to the write occurring prior to the MWAIT.
Implication: If a write to the range armed by the MONITOR instruction occurs between the
MONITOR and the MWAIT, the MWAIT instruction may start executing before the
monitoring hardware is triggered. If the MWAIT instruction causes a VM exit, this could
cause its exit qualification to incorrectly report 0x1. In the recommended usage model
for MONITOR/MWAIT, there is no write to the range armed by the MONITOR instruction
between the MONITOR and the MWAIT.
Specification Update
®
64 and IA-32 Architectures Software
21
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