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Implication: Since Intel requires that Intel Thermal Monitor be enabled in order to be operating
within specification, this erratum should never be seen during normal operation.
Workaround:Software should not disable Thermal Monitor during processor operation.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ27.
Writing the Local Vector Table (LVT) When an Interrupt Is Pending
May Cause an Unexpected Interrupt
Problem:
If a local interrupt is pending when the LVT entry is written, an interrupt may be taken
on the new interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector when a LVT entry is
written, even if the new LVT entry has the mask bit set. If there is no Interrupt Service
Routine (ISR) set up for that vector the system will GP fault. If the ISR does not do an
End of Interrupt (EOI) the bit for the vector will be left set in the in-service register and
mask all interrupts at the same or lower priority.
Workaround:Any vector programmed into an LVT entry must have an ISR associated with it, even if
that vector was programmed as masked. This ISR routine must do an EOI to clear any
unexpected interrupts that may occur. The ISR associated with the spurious vector
does not generate an EOI, therefore the spurious vector should not be used when
writing the LVT.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ28.
xAPIC Timer May Decrement Too Quickly Following an Automatic
Reload While in Periodic Mode
Problem:
When the xAPIC Timer is automatically reloaded by counting down to zero in periodic
mode, the xAPIC Timer may slip in its synchronization with the external clock. The
xAPIC timer may be shortened by up to one xAPIC timer tick.
Implication: When the xAPIC Timer is automatically reloaded by counting down to zero in periodic
mode, the xAPIC Timer may slip in its synchronization with the external clock. The
xAPIC timer may be shortened by up to one xAPIC timer tick.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ29.
Changing the Memory Type for an In-Use Page Translation May Lead
to Memory-Ordering Violations
Problem:
Under complex microarchitectural conditions, if software changes the memory type for
data being actively used and shared by multiple threads without the use of semaphores
or barriers, software may see load operations execute out of order.
Implication: Memory ordering may be violated. Intel has not observed this erratum with any
commercially-available software.
Workaround:Software should ensure pages are not being actively used before requesting their
memory type be changed.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAZ30.
Infinite Stream of Interrupts May Occur If an ExtINT Delivery Mode
Interrupt Is Received While All Cores Are in C6
Problem:
If all logical processors in a core are in C6, an ExtINT delivery mode interrupt is
pending in the xAPIC and interrupts are blocked with EFLAGS.IF=0, the interrupt will
be processed after C6 wakeup and after interrupts are re-enabled (EFLAGS.IF=1).
However, the pending interrupt event will not be cleared.
Implication: Due to this erratum, an infinite stream of interrupts will occur on the core servicing the
external interrupt. Intel has not observed this erratum with any commercially-available
software/system.
24
Errata
Specification Update
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