Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 68

Implication: VM-entry failures that cause NMIs to become unblocked may cause the
processor to deliver an NMI to software that is not prepared for it.
Workaround: VMM software should configure the virtual-machine control structure (VMCS)
so that VM-entry failures do not occur.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI126. Benign Exception after a Double Fault May Not Cause a Triple Fault
Shutdown
According to the Intel® 64 and IA-32 Architectures Software Developer's
Problem:
Manual, Volume 3A, "Exception and Interrupt Reference", if another
exception occurs while attempting to call the double-fault handler, the
processor enters shutdown mode. However due to this erratum, only
Contributory Exceptions and Page Faults will cause a triple fault shutdown,
whereas a benign exception may not.
Implication: If a benign exception occurs while attempting to call the double-fault
handler, the processor may hang or may handle the benign exception. Intel
has not observed this erratum with any commercially available software.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI127. A VM Exit Due to a Fault While Delivering a Software Interrupt May
Save Incorrect Data into the VMCS
If a fault occurs during delivery of a software interrupt (INTn) in virtual-8086
Problem:
mode when virtual mode extensions are in effect and that fault causes a VM
exit, incorrect data may be saved into the VMCS. Specifically, information
about the software interrupt may not be reported in the IDT-vectoring
information field. In addition, the interruptibility-state field may indicate
blocking by STI or by MOV SS if such blocking were in effect before execution
of the INTn instruction or before execution of the VM-entry instruction that
injected the software interrupt.
Implication: In general, VMM software that follows the guidelines given in the section
"Handling VM Exits Due to Exceptions" of Intel® 64 and IA-32 Architectures
Software Developer's Manual Volume 3B: System Programming Guide should
not be affected. If the erratum improperly causes indication of blocking by
STI or by MOV SS, the ability of a VMM to inject an interrupt may be delayed
by one instruction.
Workaround: VMM software should follow the guidelines given in the section "Handling VM
Exits Due to Exceptions" of Intel® 64 and IA-32 Architectures Software
Developer's Manual Volume 3B: System Programming Guide.
For the steppings affected, see the Summary Tables of Changes.
Status:
68 Intel
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
®
Core™2 Extreme Processor X6800 and
Specification Update
Errata