Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 35

Errata
When a far transfer switches the processor from 32-bit mode to IA-32e
Problem:
mode, the upper 32 bits of the 'From' (source) addresses reported through
the BTMs (Branch Trace Messages) or BTSs (Branch Trace Stores) may be
incorrect.
Implication: The upper 32 bits of the 'From' address debug information reported through
BTMs or BTSs may be incorrect during this transition
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI33. Unsynchronized Cross-Modifying Code Operations Can Cause
Unexpected Instruction Execution Results
The act of one processor, or system bus master, writing data into a currently
Problem:
executing code segment of a second processor with the intent of having the
second processor execute that data as code is called cross-modifying code
(XMC). XMC that does not force the second processor to execute a
synchronizing instruction, prior to execution of the new code, is called
unsynchronized XMC.
Software using unsynchronized XMC to modify the instruction byte stream of a
processor can see unexpected or unpredictable execution behavior from the processor
that is executing the modified code.
Implication: In this case, the phrase "unexpected or unpredictable execution behavior"
encompasses the generation of most of the exceptions listed in the Intel
Architecture Software Developer's Manual Volume 3: System Programming
Guide, including a General Protection Fault (GPF) or other unexpected
behaviors. In the event that unpredictable execution causes a GPF the
application executing the unsynchronized XMC operation would be terminated
by the operating system.
Workaround: In order to avoid this erratum, programmers should use the XMC
synchronization algorithm as detailed in the Intel Architecture Software
Developer's Manual Volume 3: System Programming Guide, Section:
Handling Self- and Cross-Modifying Code.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI34. MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum
Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data
after a Machine Check Exception (MCE)
When an MCE occurs during execution of a RDMSR instruction for MSRs
Problem:
Actual Frequency Clock Count (IA32_APERF) or Maximum Frequency Clock
Count (IA32_MPERF), the current and subsequent RDMSR instructions for
these MSRs may contain incorrect data.
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
35