Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 40

If a SYSCALL instruction follows immediately after EFLAGS.TF was updated
Problem:
and IA32_FMASK.TF (bit 8) is cleared, then under certain circumstances
SYSCALL may behave according to the previous EFLAGS.TF.
Implication: When the problem occurs, SYSCALL may generate an unexpected debug
exception, or may skip an expected debug exception.
Workaround: Mask EFLAGS.TF by setting IA32_FMASK.TF (bit 8).
For the steppings affected, see the Summary Tables of Changes.
Status:
AI48. Code Segment Limit/Canonical Faults on RSM May be Serviced before
Higher Priority Interrupts/Exceptions
Normally, when the processor encounters a Segment Limit or Canonical Fault
Problem:
due to code execution, a #GP (General Protection Exception) fault is
generated after all higher priority Interrupts and exceptions are serviced. Due
to this erratum, if RSM (Resume from System Management Mode) returns to
execution flow that results in a Code Segment Limit or Canonical Fault, the
#GP fault may be serviced before a higher priority Interrupt or Exception
(e.g. NMI (Non-Maskable Interrupt), Debug break (#DB), Machine Check
(#MC), etc.)
Implication: Operating systems may observe a #GP fault being serviced before higher
priority Interrupts and Exceptions. Intel has not observed this erratum on any
commercially available software.
Workaround: None Identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI49. VM Bit is Cleared on Second Fault Handled by Task Switch from
Virtual-8086 (VM86)
Following a task switch to any fault handler that was initiated while the
Problem:
processor was in VM86 mode, if there is an additional fault while servicing the
original task switch then the VM bit will be incorrectly cleared in EFLAGS, data
segments will not be pushed and the processor will not return to the correct
mode upon completion of the second fault handler via IRET.
Implication: When the OS recovers from the second fault handler, the processor will no
longer be in VM86 mode. Normally, operating systems should prevent
interrupt task switches from faulting, thus the scenario should not occur
under normal circumstances.
Workaround: None Identified
For the steppings affected, see the Summary Tables of Changes.
Status:
AI50. IA32_FMASK is Reset during an INIT
IA32_FMASK MSR (0xC0000084) is reset during INIT.
Problem:
40 Intel
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
®
Core™2 Extreme Processor X6800 and
Specification Update
Errata