Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 34

AI30. (E)CX May Get Incorrectly Updated When Performing Fast String REP
MOVS or Fast String REP STOS With Large Data Structures
When performing Fast String REP MOVS or REP STOS commands with data
Problem:
structures [(E)CX*Data Size] larger than the supported address size structure
(64K for 16-bit address size and 4G for 32-bit address size) some addresses
may be processed more than once. After an amount of data greater than or
equal to the address size structure has been processed, external events (such
as interrupts) will cause the (E)CX registers to be increment by a value that
corresponds to 64K bytes for 16 bit address size and 4G bytes for 32 bit
address size.
Implication: (E)CX may contain an incorrect count which may cause some of the MOVS or
STOS operations to re-execute. Intel has not observed this erratum with any
commercially available software.
Workaround: Do not use values in (E)CX that when multiplied by the data size give values
larger than the address space size (64K for 16-bit address size and 4G for
32-bit address size).
For the steppings affected, see the Summary Tables of Changes.
Status:
AI31. Performance Monitoring Events for Retired Loads (CBH) and
Instructions Retired (C0H) May Not Be Accurate
The following events may be counted as instructions that contain a load by
Problem:
the MEM_LOAD_RETIRED performance monitor events and may be counted
as loads by the INST_RETIRED (mask 01H) performance monitor event:
• Prefetch instructions
• x87 exceptions on FST* and FBSTP instructions
• Breakpoint matches on loads, stores, and I/O instructions
• Stores which update the A and D bits
• Stores that split across a cache line
• VMX transitions
• Any instruction fetch that misses in the ITLB
Implication: The MEM_LOAD_RETIRED and INST_RETIRED (mask 01H) performance
monitor events may count a value higher than expected. The extent to which
the values are higher than expected is determined by the frequency of the
above events.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI32. Upper 32 bits of 'From' Address Reported through BTMs or BTSs May
be Incorrect
34 Intel
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
®
Core™2 Extreme Processor X6800 and
Specification Update
Errata