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Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification

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®
Intel
Core
Δ
E8000
and E7000

Specification Update

— on 45 nm Process in the 775-land LGA Package
July 2010
®
Notice: The Intel
Core
errata which may cause the product to deviate from published specifications. Current
characterized errata are documented in this Specification Update.
™
2 Duo Processor
TM
2 Duo processor may contain design defects or errors known as
Δ
Series
Document Number: 318733-018

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Summary of Contents for Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010

  • Page 1: Specification Update

    — on 45 nm Process in the 775-land LGA Package July 2010 ® Notice: The Intel Core 2 Duo processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
  • Page 2 Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

  • Page 3: Table Of Contents

    Preface ..........................6 Summary Tables of Changes ....................8 Identification Information ...................... 14 Component Identification Information ..................15 Errata..........................18 Specification Changes ......................48 Specification Clarifications ..................... 49 Documentation Changes ......................50 § ® ™ Intel Core 2 Duo Processor Specification Update...

  • Page 4: Revision History

    Revision History Revision Description Date Number ® ™ Initial release of Intel Core 2 Duo Desktop Processor E8000 Jan 7 2008 Series Specification Update • Added Erratum AW51 Feb 1 2008 • Added Errata AW52 to AW54 Feb 13 2008 •...
  • Page 5 Number July 15 2009 • Added Errata AW77 and AW78 • Added Errata AW79 March 16 , 2010 • Added Errata AW80 July 19 , 2010 • Removed Item Numbering Section ® ™ Intel Core 2 Duo Processor Specification Update...

  • Page 6: Preface

    This document may also contain information that has not been previously published. Affected Documents Document Title Document Number 318732 ® ™ Intel Core 2 Duo Processor E8000 and E7000 Series Datasheet Rev 006 Related Documents Document Title Document Location ®...
  • Page 7 Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, etc.). § ® ™ Intel Core 2 Duo Processor Specification Update...

  • Page 8: Summary Tables Of Changes

    The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
  • Page 9 Summary Tables of Changes ® ® The Specification Updates for the Pentium processor, Pentium Pro processor, and other Intel products do not use this convention. ERRATA Plan EFLAGS Discrepancy on Page Faults after a Translation No Fix Change INVLPG Operation for Large (2M/4M) Pages May be...
  • Page 10 Instruction Fetch May Cause a Livelock During Snoops of AW38 No Fix the L1 Data Cache Use of Memory Aliasing with Inconsistent Memory Type AW39 No Fix may Cause a System Hang or a Machine Check Exception ® ™ Intel Core 2 Duo Processor Specification Update...
  • Page 11 Alignment Check Exception AW58 Plan Fix PSI# Signal Asserted During Reset Thermal Interrupts are Dropped During and While Exiting AW59 No Fix ® Intel Deep Power-Down State VM Entry May Fail When Attempting to Set AW60 No Fix IA32_DEBUGCTL.FREEZE_WHILE_SMM_EN ® ™...
  • Page 12 Global Instruction TLB Entries May Not be Invalidated on a AW65 No Fix VM Exit or VM Entry ® When Intel Deep Power-Down State is Being Used, AW66 No Fix IA32_FIXED_CTR2 May Return Incorrect Cycle Counts Enabling PECI via the PECI_CTL MSR incorrectly...
  • Page 13 Summary Tables of Changes Number SPECIFICATION CLARIFICATIONS Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Number DOCUMENTATION CHANGES There are no Documentation Changes in this Specification Update revision. § ® ™ Intel Core 2 Duo Processor Specification Update...

  • Page 14: Identification Information

    Identification Information Identification Information Figure 1. Processor Package Example § ® ™ Intel Core 2 Duo Processor Specification Update...

  • Page 15: Component Identification Information

    Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register. Refer to the Intel Processor Identification and the CPUID Instruction Application Note (AP-485) and the Wolfdale Family Processor Family BIOS Writer’s Guide (BWG) for further information on the CPUID instruction.

  • Page 16: Component Identification Information

    2. These parts support Intel 3. These parts support Execute Disable Bit Feature ® ® 4. These parts support Intel Virtualization Technology (Intel 5. These parts have Intel® Trusted Execution Technology (Intel® TXT) enabled 6. These parts have PROCHOT# enabled ® ™ Intel Core...
  • Page 17 8. These parts support Thermal Monitor 2 (TM2) feature 9. These parts have PECI enabled ® 10. These parts have Enhanced Intel SpeedStep Technology (EIST) enabled 11. These parts have Extended HALT State (C1E) enabled 12. These parts have Extended Stop Grant State (C2E) enabled.

  • Page 18: Errata

    VM exit or if its delivery causes a nested fault. Implication: None identified. Although the EFLAGS value saved may contain incorrect arithmetic flag values, Intel has not identified software that is affected by this erratum. This erratum will have no further effects once the original instruction is restarted because the instruction will produce the same results as if it had initially completed without a page fault.
  • Page 19 Implication: Software that uses non-temporal data without proper serialization before accessing the non-temporal data may observe data in wrong program order. Workaround: Software that conforms to the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, section “Buffering of Write Combining Memory Locations”...
  • Page 20 Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software.
  • Page 21 #GP fault (general protection exception). Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 22 0x0. Implication: This is a rare condition that may result in a system hang. Intel has not observed this erratum with any commercially available software, or system.
  • Page 23 Under certain conditions as described in the Software Developers Manual Problem: section “Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors” the processor performs REP MOVS or REP STOS as fast strings. Due to this erratum fast string REP MOVS/REP STOS instructions...
  • Page 24 Exception (e.g. NMI (Non-Maskable Interrupt), Debug break(#DB), Machine Check (#MC), etc.) Implication: Operating systems may observe a #GP fault being serviced before higher priority Interrupts and Exceptions. Intel has not observed this erratum on any commercially available software. Workaround: None identified.
  • Page 25 HLT or MWAIT events, are also not counted: a) RSM from a C-state SMI during an MWAIT instruction. b) RSM from an SMI during a HLT instruction. ® ™ Intel Core 2 Duo Processor Specification Update...
  • Page 26 SMRAM may result in unpredictable system behavior. Implication: If SMM software changes the values of the EFLAGS.VM in SMRAM, it may result in unpredictable system behavior. Intel has not observed this behavior in commercially available software. Workaround: SMM software should not change the value of EFLAGS.VM in SMRAM.
  • Page 27 #MF. In this situation, the interrupt should be serviced before the #MF. Because of this erratum, if following STI, an instruction that triggers a #MF is executed while STPCLK#, Enhanced Intel SpeedStep® Technology transitions or Thermal Monitor 1 events occur, the pending #MF may be serviced before higher priority interrupts.
  • Page 28 Software which is written so that multiple agents can modify the same shared Problem: unaligned memory location at the same time may experience a memory ordering issue if multiple loads access this shared data shortly thereafter. ® ™ Intel Core 2 Duo Processor Specification Update...
  • Page 29 Exposure to this problem requires the use of a data write which spans a cache line boundary. Implication: This erratum may cause loads to be observed out of order. Intel has not observed this erratum with any commercially available software or system.
  • Page 30 Implication: Software will observe an incorrect version number in CPUID.0Ah.EAX [7:0] in comparison to which features are actually supported. Workaround: Software should use the recommended enumeration mechanism described in the Architectural Performance Monitoring section of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3: System Programming Guide.
  • Page 31 Problem: multiple level one data cache snoops. Implication: Due to this erratum, a livelock may occur. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for BIOS to contain a workaround for this erratum.
  • Page 32 Blocking by MOV/POP SS and Blocking by STI Bits to be Cleared in the Guest Interruptibility-State Field As specified in Section, “VM Exits Induced by the TPR Shadow”, in the Intel® Problem: 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, a VM exit occurs immediately after any VM entry performed with the “use TPR...
  • Page 33 WC memory operations. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Intel does not support the use of cacheable and WC memory type aliasing, and WC operations are defined as weakly ordered.
  • Page 34 (MOVNTDQA) are mixed with non-streaming loads that split across cache lines, the processor may hang. Implication: Under the scenario described above, the processor may hang. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
  • Page 35 Implication: The cacheline split load operation may not be able to complete normally, and the machine may hang and generate Machine Check Exception. Intel has not observed this erratum with any commercially available software.
  • Page 36 Implication: If a benign exception occurs while attempting to call the double-fault handler, the processor may hang or may handle the benign exception. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 37 Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]SP, [r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any exception. Intel has not observed this erratum with any commercially available software, or system.
  • Page 38 Implication: In general, VMM software that follows the guidelines given in the section “Handling VM Exits Due to Exceptions” of Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B: System Programming Guide should not be affected. If the erratum improperly causes indication of blocking by STI or by MOV SS, the ability of a VMM to inject an interrupt may be delayed by one instruction.
  • Page 39 Thermal interrupts are ignored while the processor is in Intel Deep Power- Problem: Down State as well as during a small window of time while exiting from Intel Deep Power-Down State. During this window, if the PROCHOT signal is driven or the internal value of the sensor reaches the programmed thermal trip point, then the associated thermal interrupt may be lost.
  • Page 40 Problem: guest-state area of the VMCS, VM entry may fail as described in Section “VM- ® Entry Failures During or After Loading Guest State” of Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3B: System Programming Guide, Part 2. (The exit reason will be 80000021H and the exit qualification will be zero.) Note that the FREEZE_WHILE_SMM_EN bit in the guest...
  • Page 41 Implication: Stale global instruction linear to physical page translations may be used by a VMM after a VM exit or a guest after a VM entry. ® ™ Intel Core 2 Duo Processor Specification Update...
  • Page 42 Implication: If software programs a value in IA32_LSTAR to be used by the SYSCALL instruction and the processor subsequently receives an INIT reset, the SYSCALL instructions will not behave as intended. Intel has not observed this erratum in any commercially available software.
  • Page 43 Implication: The corruption of the bottom two bits of the CS segment register will have no impact unless software explicitly examines the CS segment register between enabling protected mode and the first far JMP. Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section titled "Switching to Protected Mode"...
  • Page 44 Implication: Execution of the stores in XSAVE, when XSAVE is used to store SSE context only, may not follow program order and may execute before older stores. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 45 A Page Fault May Not be Generated When the PS bit is set to “1” in a PML4E or PDPTE On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7) Problem: is reserved in PML4Es and PDPTEs. If the translation of the linear address of a memory access encounters a PML4E or a PDPTE with PS set to 1, a page fault should occur.
  • Page 46 Implication: Software may erroneously infer that a page fault was due to a reserved-bit violation when it was actually due to an attempt to access a not-present page. Intel has not observed this erratum with any commercially available software. Workaround: Page-fault handlers should ignore the RSVD flag in the error code if the P flag is 0.
  • Page 47 VMCS. Implication: Due to this erratum, VM entry may result in the wrong value being loaded into the IA32_DEBUGCTL MSR. Intel has not observed this erratum with any commercially available software. Workaround: Software seeking to load the IA32_DEBUGCTL MSR as part of VM entry should place the desired value in the guest IA32_DEBUGCTL field in the VMCS and set the “load debug controls”...

  • Page 48: Specification Changes

    Specification Changes Specification Changes The Specification Changes listed in this section apply to the following documents: ® ™ • Intel Core 2 Duo Processor E8000 and E7000 Series Datasheet ® • Intel 64 and IA-32 Architectures Software Developer’s Manual volumes 1,2A, 2B,...

  • Page 49: Specification Clarifications

    Intel processors implement. This information is needed to aid operating systems in managing page table structure invalidations properly. Intel will update the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide in the coming months. Until that time, an application note, TLBs, Paging-Structure Caches, and Their Invalidation (http://www.intel.com/products/processor/manuals/index.htm),...

  • Page 50: Documentation Changes

    64 and IA-32 Architectures Software Developer’s ® Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document Intel 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes. Follow the link below to become familiar with this file.

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