Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 16

NO B1 B2 L2
AI118 X X X
AI119 X X X
AI120 X X X
AI121
AI122
AI123
AI124 X X X
AI125 X X X
AI126 X X X
AI127 X X X
AI128 X X X
Number
- There are no Specification Changes in this Specification Update revision.
Number
AI1 Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation
Number
- There are no Documentation Changes in this Specification Update revision.
16
M0 G0 Plan ERRATA
VM Exit with Exit Reason "TPR Below Threshold" Can Cause the Blocking
X X No Fix by MOV/POP SS and Blocking by STI Bits to be Cleared in the Guest
Interruptibility-State Field
Using Memory Type Aliasing with Cacheable and WC Memory Types May
X X No Fix
Lead to Memory Ordering Violations
X X No Fix VM Exit due to Virtual APIC-Access May Clear RF
Fixed Function Performance Counters MSR_PERF_FIXED_CTR1 (30AH)
X Fixed and MSR_PERF_FIXED_CTR2 (30BH) are Not Cleared When the
Processor is Reset
X Fixed VTPR Access May Lead to System Hang
IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check Error
X Fixed
Reporting Enable Correctly
RSM Instruction Execution under Certain Conditions May Cause
X X No Fix
Processor Hang or Unexpected Instruction Execution Results
Fixed NMIs May Not Be Blocked by a VM-Entry Failure
Benign Exception after a Double Fault May Not Cause a Triple Fault
X X No Fix
Shutdown
A VM Exit Due to a Fault While Delivering a Software Interrupt May
X X No Fix
Save Incorrect Data into the VMCS
A VM Exit Occuring in IA-32e Mode May Not Produce a VMX Abort When
X X No Fix
Expected
SPECIFICATION CHANGES
SPECIFICATION CLARIFICATIONS
DOCUMENTATION CHANGES
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Summary Tables of Changes
§
®
Intel Core™2 Extreme Processor X6800 and
Specification Update