Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 67

Errata
Implication: Software running VMX non-root operation may cause a logical processor to
hang if the virtual-machine monitor (VMM) sets both the "use TPR shadow"
and "virtualize APIC accesses" VM-execution controls.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI123. IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check
Error Reporting Enable Correctly
IA32_MC1_STATUS MSR (405H) bit[60] (EN- Error Enabled) is supposed to
Problem:
indicate whether the enable bit in the IA32_MC1_CTL MSR (404H) was set at
the time of the last update to the IA32_MC1_STATUS MSR. Due to this
erratum, IA32_MC1_STATUS MSR bit[60] instead reports the current value of
the IA32_MC1_CTL MSR enable bit.
Implication: IA32_MC1_STATUS MSR bit [60] may not reflect the correct state of the
enable bit in the IA32_MC1_CTL MSR at the time of the last update.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI124. RSM Instruction Execution under Certain Conditions May Cause
Processor Hang or Unexpected Instruction Execution Results
RSM instruction execution, under certain conditions triggered by a complex
Problem:
sequence of internal processor micro-architectural events, may lead to
processor hang, or unexpected instruction execution results.
Implication: In the above sequence, the processor may live lock or hang, or RSM
instruction may restart the interrupted processor context through a
nondeterministic EIP offset in the code segment, resulting in unexpected
instruction execution, unexpected exceptions or system hang. Intel has not
observed this erratum with any commercially available software.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI125. NMIs May Not Be Blocked by a VM-Entry Failure
The Intel® 64 and IA-32 Architectures Software Developer's Manual Volume
Problem:
3B: System Programming Guide, Part 2 specifies that, following a VM-entry
failure during or after loading guest state, "the state of blocking by NMI is
what it was before VM entry." If non-maskable interrupts (NMIs) are blocked
and the "virtual NMIs" VM-execution control set to 1, this erratum may result
in NMIs not being blocked after a VM-entry failure during or after loading
guest state.
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
67