Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 57

Errata
Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL (Event select
Problem:
0B3H, Umask 01H) counts the number of SIMD packed multiply micro-ops
executed. The count for PMULUDQ micro-ops may be lower than expected.
No other instruction is affected.
Implication: The count value returned by the performance monitoring event
SIMD_UOP_TYPE_EXEC.MUL may be lower than expected. The degree of
undercount depends on actual occurrences of PMULUDQ instructions, while
the counter is active.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI97. Storage of PEBS Record Delayed Following Execution of MOV SS or
STI
When a performance monitoring counter is configured for PEBS (Precise
Problem:
Event Based Sampling), overflow of the counter results in storage of a PEBS
record in the PEBS buffer. The information in the PEBS record represents the
state of the next instruction to be executed following the counter overflow.
Due to this erratum, if the counter overflow occurs after execution of either
MOV SS or STI, storage of the PEBS record is delayed by one instruction.
Implication: When this erratum occurs, software may observe storage of the PEBS record
being delayed by one instruction following execution of MOV SS or STI. The
state information in the PEBS record will also reflect the one instruction delay.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI98. Store Ordering May be Incorrect between WC and WP Memory Types
According to Intel
Problem:
Volume 3A "Methods of Caching Available", WP (Write Protected) stores
should drain the WC (Write Combining) buffers in the same way as UC
(Uncacheable) memory type stores do. Due to this erratum, WP stores may
not drain the WC buffers.
Implication: Memory ordering may be violated between WC and WP stores.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI99. Updating Code Page Directory Attributes without TLB Invalidation
May Result in Improper Handling of Code #PF
Code #PF (Page Fault exception) is normally handled in lower priority order
Problem:
relative to both code #DB (Debug Exception) and code Segment Limit
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
®
64 and IA-32 Architectures Software Developer's Manual,
57