Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 38

Implication: Due to this erratum, the processor may livelock.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI41. PREFETCHh Instructions May Not be Executed when Alignment Check
(AC) is Enabled
PREFETCHT0, PREFETCHT1, PREFETCHT2 and PREFETCHNTA instructions may
Problem:
not be executed when Alignment Check is enabled.
Implication: PREFETCHh instructions may not perform the data prefetch if Alignment
Check is enabled.
Workaround: Clear the AC flag (bit 18) in the EFLAGS register and/or the AM bit (bit 18) of
Control Register CR0 to disable alignment checking.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI42. Upper 32 Bits of the FPU Data (Operand) Pointer in the FXSAVE
Memory Image May Be Unexpectedly All 1's after FXSAVE
The upper 32 bits of the FPU Data (Operand) Pointer may incorrectly be set
Problem:
to all 1's instead of the expected value of all 0's in the FXSAVE memory
image if all of the following conditions are true:
• The processor is in 64-bit mode.
• The last floating point operation was in compatibility mode
• Bit 31 of the FPU Data (Operand) Pointer is set.
• An FXSAVE instruction is executed
Implication: Software depending on the full FPU Data (Operand) Pointer may behave
unpredictably.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI43. Concurrent Multi-processor Writes to Non-dirty Page May Result in
Unpredictable Behavior
When a logical processor writes to a non-dirty page, and another logical-
Problem:
processor either writes to the same non-dirty page or explicitly sets the dirty
bit in the corresponding page table entry, complex interaction with internal
processor activity may cause unpredictable system behavior.
Implication: This erratum may result in unpredictable system behavior and hang.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
38 Intel
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
®
Core™2 Extreme Processor X6800 and
Specification Update
Errata