Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification
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Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification

Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification

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®
Intel
Core
Δ
X6800
and Intel
Desktop Processor E6000
Δ
E4000
Sequence
Specification Update
— on 65 nm Process in the 775-land LGA Package supporting
®
Φ
Intel
64
Architecture, Intel
®
Intel
Trusted Execution Technologyŧ
May 2008
Notice: The Intel
contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are documented in
this Specification Update.
™
2 Extreme Processor
®
®
TM
Core
2 Extreme and Intel
®
™
Core
2 Duo
Virtualization Technology± and
®
TM
Core
2 Duo desktop processor may
Document Number:
Δ
and
313279-026

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Summary of Contents for Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008

  • Page 1 ® ® Notice: The Intel Core 2 Extreme and Intel Core 2 Duo desktop processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
  • Page 2 The Intel cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. ® Φ Intel 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64.

  • Page 3: Table Of Contents

    Summary Tables of Changes ....................8 Identification Information ....................17 Component Identification Information..................20 Errata ..........................23 Specification Changes ......................70 Specification Clarifications ....................71 Documentation Changes ......................72 § ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...

  • Page 4: Revision History

    • Added processor number E6320, E6420 and E4400 information Apr 2007 -012 Out Of Cycle • Added Erratum AI105 Apr 2007 -013 Out Of Cycle ® Intel Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 5 Erratum -025 • Added processor number E4700 information Mar 3 2008 -026 • Added Erratum AI127, AI128 May 2008 ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...

  • Page 6: Preface

    64 and IA-32 Architectures Software Developer’s Manual Volume 3A: System Programming Guide ® Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3B: System Programming Guide ® Intel Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 7 (datasheets, manuals, etc.). § ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence...

  • Page 8: Summary Tables Of Changes

    The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
  • Page 9 Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) Mobile Intel® Pentium® 4 processor-M 64-bit Intel®...
  • Page 10 Intel® Core™ 2 Duo processor E8000 series AX = Quad-Core Intel® Xeon® processor 5400 series Dual-Core Intel® Xeon® processor 5200 series Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45- AZ = nm Process AAA = Quad-Core Intel® Xeon® processor 3300 series AAB = Dual-Core Intel®...
  • Page 11 EIP May be Incorrect after Shutdown in IA-32e Mode #GP Fault is Not Generated on Writing IA32_MISC_ENABLE [34] When AI29 No Fix Execute Disable Bit is Not Supported ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 12 VM Bit is Cleared on Second Fault Handled by Task Switch from Virtual- AI49 No Fix 8086 (VM86) AI50 Fixed IA32_FMASK is Reset during an INIT ® Intel Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 13 PMI May Be Delayed to Next PEBS Event PEBS Buffer Overflow Status Will Not be Indicated Unless AI72 Fixed IA32_DEBUGCTL[12] is Set ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 14 Count Some Decoded Instructions The Stack Size May be Incorrect as a Result of VIP/VIF Check on AI95 Fixed SYSEXIT and SYSRET ® Intel Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 15 VMCALL failure due to corrupt MSEG location may cause VM Exit to load AI108 Fixed the machine state incorrectly Overlap of an Intel® VT APIC Access Page in a Guest with the DS Save AI109 Fixed Area May Lead to Unpredictable Behavior...
  • Page 16 SPECIFICATION CLARIFICATIONS Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Number DOCUMENTATION CHANGES There are no Documentation Changes in this Specification Update revision. § ® Intel Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...

  • Page 17: Identification Information

    Identification Information Identification Information ® Figure 1. Intel Core™2 Duo Desktop Processor 2M SKU Package with 800 MHz FSB ® Figure 2. Intel Core™2 Duo Desktop Processor 2M SKU Package with 1066 MHz FSB ® Intel Core™2 Extreme Processor X6800 and ®...
  • Page 18 Core™2 Duo Desktop Processor 4M SKU Package with 1066 MHz FSB ® Figure 4. Intel Core™2 Duo Desktop Processor 4M SKU Package with 1333 MHz FSB ® Intel Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 19 Identification Information ® Figure 5. Intel Core™2 Extreme Processor Package § ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...

  • Page 20: Component Identification Information

    Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register. Refer to the Intel Processor Identification and the CPUID Instruction Application Note (AP-485) Conroe and Woodcrest Processor Family BIOS Writer’s Guide (BWG)
  • Page 21 Component Identification Information ® Table 1. Intel Core™2 Duo Desktop Processor 2M SKU Identification Information L2 Cache Core Processor Processor Speed S-Spec Size Package Notes Stepping Signature Number Core/Bus (bytes) 1.86 GHz / 1, 3, 4, 6, 7, 8, 9,...
  • Page 22 2.93 GHz / 2, 3, 4, 6, 7, 8, 9, SL9S5 06F6h X6800 775-land LGA 1066 MHz 10, 11, 12, 13, 15 ® Intel Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...

  • Page 23: Errata

    DEFER# is received during a snoop phase and the Locked transaction is pipelined on the front side bus (FSB), LOCK# may unexpectedly de-assert. Implication: When this erratum occurs, the system may hang during shutdown. Intel has not observed this erratum with any commercially available systems or software.
  • Page 24 SYSCALL instruction). Due to this erratum, the RFLAGS.RF bit will be unconditionally cleared after execution of the SYSRET instruction. ® Intel Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 25 Errata Implication: The SYSRET instruction can not be used if the RF flag needs to be set after returning from a system call. Intel has not observed this erratum with any commercially available software. Workaround: Use the IRET instruction to return from a system call, if RF flag has to be set after the return.
  • Page 26 Errata Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially available software. Workaround: None Identified. For the steppings affected, see the Summary Tables of Changes.
  • Page 27 Performance Monitoring Events for Retired Instructions (C0H) May Not Be Accurate The INST_RETIRED performance monitor may miscount retired instructions Problem: as follows: ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 28 Implication: When A20M# is enabled and an address references a large page the resulting translated physical address may be incorrect. This erratum has not been observed with any commercially available operating system. ® Intel Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 29 0x0. Implication: This is a rare condition that may result in a system hang. Intel has not observed this erratum with any commercially available software, or system.
  • Page 30 Workaround: Do not use global pages in system management mode. For the steppings affected, see the Summary Tables of Changes. Status: ® Intel Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 31 AI23. VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field ® Processors supporting Intel Virtualization Technology can execute VMCALL Problem: from within the Virtual Machine Monitor (VMM) to activate dual-monitor treatment of SMIs and SMM. Due to this erratum, if reserved bits are set to values inconsistent with VMX Capability MSRs, VMCALL may not VMFail.
  • Page 32 If the target of the load is to uncached memory that has a system side-effect, restarting the instruction may cause unexpected system ® Intel Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 33 Implication: Writing to IA32_MISC_ENABLE [34] bit is silently ignored without generating a fault. Workaround: None identified. For the steppings affected, see the Summary Tables of Changes. Status: ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 34 Implication: (E)CX may contain an incorrect count which may cause some of the MOVS or STOS operations to re-execute. Intel has not observed this erratum with any commercially available software. Workaround: Do not use values in (E)CX that when multiplied by the data size give values larger than the address space size (64K for 16-bit address size and 4G for 32-bit address size).
  • Page 35 Implication: In this case, the phrase "unexpected or unpredictable execution behavior" encompasses the generation of most of the exceptions listed in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide, including a General Protection Fault (GPF) or other unexpected behaviors.
  • Page 36 RCX is greater than or equal to 0X100000000. Implication: Early termination of REP CMPS/SCAS operation may be observed and RFLAGS may be incorrectly updated. ® Intel Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 37 Processor Livelock PREFETCHh instruction execution after a split load and dependent upon Problem: ongoing store operations may lead to processor livelock. ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 38 Workaround: It is possible for BIOS to contain a workaround for this erratum. For the steppings affected, see the Summary Tables of Changes. Status: ® Intel Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 39 For the steppings affected, see the Summary Tables of Changes. Status: AI47. SYSCALL Immediately after Changing EFLAGS.TF May Not Behave According to the New EFLAGS.TF ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 40 (e.g. NMI (Non-Maskable Interrupt), Debug break (#DB), Machine Check (#MC), etc.) Implication: Operating systems may observe a #GP fault being serviced before higher priority Interrupts and Exceptions. Intel has not observed this erratum on any commercially available software. Workaround: None Identified.
  • Page 41 Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]SP, [r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any exception. Intel has not observed this erratum with any commercially available software, or system.
  • Page 42 Implication: Software that uses aliasing of WB and WT memory types may observe unpredictable behavior. Workaround: It is possible for the BIOS to contain a workaround for this erratum. ® Intel Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 43 Implication: This erratum may lead to livelock, shutdown or other unexpected processor behavior. Intel has not observed this erratum with any commercially available system. Workaround: None Identified.
  • Page 44 Under certain conditions as described in the Software Developers Manual Problem: section “Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors” the processor performs REP MOVS or REP STOS as fast strings. Due to this erratum fast string REP MOVS/REP STOS instructions...
  • Page 45 EFLAGS register on the page fault handler’s stack prematurely contains the final arithmetic flag values although the instruction has not yet completed. Intel has not identified any operating systems that inspect the arithmetic portion of the EFLAGS register during a page fault nor observed this erratum in laboratory testing of software applications.
  • Page 46 SMRAM may result in unpredictable system behavior. Implication: If SMM software changes the values of the EFLAGS.VM in SMRAM, it may result in unpredictable system behavior. Intel has not observed this behavior in commercially available software. Workaround: SMM software should not change the value of EFLAGS.VM in SMRAM.
  • Page 47 FDIV instruction with zero operand value in memory In addition, an assist event may be counted when DAZ (Denormals-Are-Zeros) and FTZ (Flush-To-Zero) flags are turned on even though no actual assist occurs. ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence...
  • Page 48 Implication: Debug Store Interrupt Service Routines may observe delay of PMI occurrence by one PEBS event. Workaround: None identified. For the steppings affected, see the Summary Tables of Changes. Status: ® Intel Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 49 TSS (Task State Segment), and will not be used. Workaround: Use an interrupt task gate for the machine check handler. For the steppings affected, see the Summary Tables of Changes. Status: ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence...
  • Page 50 Implication: A BTM/BTS branch-from instruction address may get corrupted for software interrupts. Workaround: None identified. For the steppings affected, see the Summary Tables of Changes. Status: ® Intel Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 51 When data of Store to WT memory is used by two subsequent loads of one Problem: thread and another thread performs cacheable write to the same address the ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence...
  • Page 52 16 bit operand size (REX.W =0 and 66H prefix) will only store 16 bits and leave bits 63:16 at the destination register unmodified, instead of storing zeros in them. Implication: Intel has not observed this erratum with any commercially available software. Workaround: None identified. For the steppings affected, see the Summary Tables of Changes.
  • Page 53 Basic Architecture, for information on the usage of the ENTER instructions. This erratum is not expected to occur in ring 3. Faults are usually processed in ring 0 and stack switch occurs when transferring to ring 0. Intel has not observed this erratum on any commercially available software.
  • Page 54 A or D bits being set in a Page Table Entry (PTE)) Implication: Stale translations may remain valid in TLB after a PTE update resulting in unpredictable system behavior. Intel has not observed this erratum with any commercially available software.
  • Page 55 (due to redundant prefixes placed before the instruction) may lead, under complex circumstances, to unexpected behavior. Implication: The processor may behave unexpectedly due to invalid instructions. Intel has not observed this erratum with any commercially available software.
  • Page 56 LSD (Loop Stream Detector), as described in the Optimizing the Front End section of the Intel® 64 and IA-32 Architectures Optimization Reference Manual.
  • Page 57 Status: AI98. Store Ordering May be Incorrect between WC and WP Memory Types ® According to Intel 64 and IA-32 Architectures Software Developer’s Manual, Problem: Volume 3A "Methods of Caching Available", WP (Write Protected) stores should drain the WC (Write Combining) buffers in the same way as UC (Uncacheable) memory type stores do.
  • Page 58 CPU_CLK_UNHALTED.REF event count to the maximum resolved boot frequency using this ratio. For the steppings affected, see the Summary Tables of Changes. Status: ® Intel Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
  • Page 59 Implication: (E)CX may contain an incorrect count which may cause some of the STOS operations to re-execute. Intel has not observed this erratum with any commercially available software. Workaround: Do not use values in (E)CX that when multiplied by the data size give values larger than the address space size (64K for 16-bit address size and 4G for 32-bit address size).
  • Page 60 As an example, an access to a memory mapped I/O device may be incorrectly marked as cacheable, become cached, and never make it to the I/O device. Intel has not observed this erratum with any commercially available software.
  • Page 61 For the steppings affected, see the Summary Tables of Changes. Status: AI109. Overlap of an Intel® VT APIC Access Page in a Guest with the DS Save Area May Lead to Unpredictable Behavior Logging of a branch record or a PEBS (precise-event-based-sampling) record...
  • Page 62 APIC access page to avoid such an overlap. Under normal circumstances for correctly written software, such an overlap is not expected to exist. Intel has not observed this erratum with any commercially available software. Workaround: For a fully comprehensive workaround, the VMM should not allow the logging of branch or PEBS records while guest software is running if the "virtualize...
  • Page 63 Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software.
  • Page 64 Problem: multiple level one data cache snoops. Implication: Due to this erratum, a livelock may occur. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for BIOS to contain a workaround for this erratum.
  • Page 65 Blocking by MOV/POP SS and Blocking by STI Bits to be Cleared in the Guest Interruptibility-State Field As specified in Section, “VM Exits Induced by the TPR Shadow”, in the Intel® Problem: 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, a VM exit occurs immediately after any VM entry performed with the “use TPR...
  • Page 66 WC memory operations. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Intel does not support the use of cacheable and WC memory type aliasing, and WC operations are defined as weakly ordered.
  • Page 67 EIP offset in the code segment, resulting in unexpected instruction execution, unexpected exceptions or system hang. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
  • Page 68 Implication: If a benign exception occurs while attempting to call the double-fault handler, the processor may hang or may handle the benign exception. Intel has not observed this erratum with any commercially available software.
  • Page 69 VM-exit control is 1 in the executive VMCS. For the steppings affected, see the Summary Tables of Changes. Status: § ® Intel Core™2 Extreme Processor X6800 and ® Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...

  • Page 70: Specification Changes

    Core™2 Duo desktop processor documentation. Δ Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature.

  • Page 71: Specification Clarifications

    Specification Clarifications Specification Clarifications The Specification Clarifications listed in this section apply to the following documents: • Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Datasheet ® • Intel 64 and IA-32 Architectures Software Developer’s Manual volumes 1, 2A,...

  • Page 72: Documentation Changes

    64 and IA-32 Architectures Software Developer’s ® Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document Intel 64 and IA-32 Architectures Software Developer’s manual documentation changes. Follow the link below to become familiar with this file.

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