Figure 126 - The If Register - Nintendo GAME BOY ADVANCE Programming Manual

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15.3 Interrupt Request Register
When an interrupt request signal is generated from each hardware device, the corresponding interrupt
request flag is set in the IF Register.
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Address Register
202h IF
If a 1 is written to the bit which the interrupt request flag is set in, that interrupt request flag can be reset.
15.3.1 About H-Blank Interrupts
H-Blank interrupt requests also occur during V-Blank.
15.3.2 About Game Pak Interrupts
An interrupt request occurs when the IREQ terminal is "High".
Although the IREQ terminal is pulled "High" in the Game Boy Advance hardware, the IREQ terminal is set
to "Lo" when a normal Game Pak is installed. Therefore, the IREQ terminal is pulled "High" and an interrupt
request occurs when the Game Pak is removed from the Game Boy Advance.
15.3.3 Cautions Regarding Clearing IME and IE
A corresponding interrupt could occur even while a command to clear IME or each flag of the IE register is
being executed.
When clearing a flag of IE, you need to clear IME in advance so that mismatching of interrupt checks will
not occur.
When Multiple Interrupts are Used
When the timing of clearing of IME and the timing of an interrupt agree, multiple interrupts will not occur
during that interrupt. Therefore, set (enable) IME after saving IME during the interrupt routine.
15.3.4 Other Cautions
The CPU stops during DMA transfer. Therefore, interrupts cannot take place until the DMA transfer has
completed (there is a delay until the DMA has finished).
AGB-06-0001-002-B13
Released: May 27, 2005
Game Boy Advance Programming Manual
Figure 126 - The IF Register
DMA DMA DMA DMA
Timer
3 2 1 0 3
Serial Communication/General Purpose
Communication/UART Communication
DMA
Key
Game Pak(DREQ/IREQ)
Attributes Initial Value
Timer Timer Timer
R
H V
2 1 0
Rendering Blank
V Counter Matching
Timer
Communication/JOY Bus
© 1999-2005 NINTENDO
May 25, 2005
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