Figure 90 - Dma 1 And 2 Control Registers - Nintendo GAME BOY ADVANCE Programming Manual

May 25, 2005
12.2.4 DMA Control
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Address Register
0C6h DMA1CNT_H
0D2h
DMA2CNT_H
DMA(1,2)CNT_H [d15] DMA Enable Flag
A setting of 0 disables the DMA function.
A setting of 1 enables DMA, and after the transfer is completed the source and destination registers
are restored to their last values.
Delay of 2 waits will occur before DMA is activated after this flag is set. Accessing DMA related
Note:
registers during this time may cause a DMA malfunction. Do another process or insert a
dummy load command instead.
DMA(1,2)CNT_H [d14] Interrupt Request Enable Flag
Enables an interrupt request to be generated when DMA transfer of the specified word count has been
completed.
No request is generated with a setting of 0; a request is generated with a setting of 1.
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DMA 1 and 2

Figure 90 - DMA 1 and 2 Control Registers

DMA Transfer Type
0: 16-bit Transfer
1: 32-bit Transfer
DMA Start Timing
00: Start Immediately
01: Start in a V-blank Interval
10: Start in an H-blank Interval
11: Prohibited Code
Interrupt Request Enable Flag
0: Disable
1: Enable
DMA Enable Flag
0: OFF
1: ON
Destination Address Control Flag
00: Increment after Transfer
01: Decrement after Transfer
10: Fixed
11: Increment/Reload after Transfer
Source Address Control Flag
00: Increment after Transfer
01: Decrement after Transfer
10: Fixed
11: Prohibited Code
DMA Repeat
0: OFF
1: ON
97
Attributes Initial Value
R/W
0000h
AGB-06-0001-002-B13
Released: May 27, 2005