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Table 26. Processor Settings details (continued)
Option
L2 Up Down Prefetcher
MADT Core Enumeration
NUMA Nodes Per Socket
L3 cache as NUMA Domain
Secure Memory Encryption
Minimum SEV non-ES ASID
Secured Nested Paging (SNP)
SNP Memory Coverage
Transparent Secure Memory Encryption
ACPI CST C2 Latency
Configurable TDP
30
Pre-operating system management applications
Description
Enables or disables the L2 up down prefetcher. This option is
set to Enabled by default, as it optimizes overall workload.
NOTE:
This option is only available for 4
AMD EPYC processors.
Specifies the MADT Core Enumeration. This option is set to
Linear by default.
Specifies the number of NUMA nodes per socket. This option
is set to 1 by default.
The L3 carch as NUMA Domain option can be set to Enabled,
Disabled or Auto. This option is set to Disabled by default.
Enables or disables the AMD secure encryption features such
as SME and Secure Encrypted Virtualization (SEV). It also
determines if other secure encryption features such as TSME
and SEV-SNP can be enabled. This option is set to Disabled
by default.
NOTE:
This option is only available for 4
AMD EPYC processors.
Determines the number of Secure Encrypted Virtualization ES
and non-ES available Address Space IDs. This option is set to
1 by default.
Enables or disables SEV-SNP, a set of additional security
protections. This option is set to Disabled by default.
This option selects the operating mode of the Nested Paging
(SNP) Memory and the reverse Map Table(RMP). The RMP
is used to ensure a one-to-one mapping between system
physical addresses and guest physical addresses
Enables or disables the TSME. TSME is always-on memory
encryption that does not require OS or hypervisor support.
This option is set to Disabled by default.
● If the OS supports SME, do not enable this field.
● If the hypervisor supports SEV, do not enable this field.
Enabling
TSME affects the system memory performance.
Enter in 18-1000 microseconds (decimal value). Larger C2
latency values will reduce the number of C2 transitions
and reduce C2 residency. Fewer transitions can help when
performance is sensitive to the latency of C2 entry and exit.
Higher residency can improve performance by allowing higher
frequency boost and reduce idle core power. With Linux kernel
6.0 or later, the C2 transition cost is significantly reduced. The
best value will be dependent on kernel version, use case, and
workload.
Allows the reconfiguration of the processor Thermal Design
Power (TDP) levels based on the power and thermal delivery
capabilities of the system. TDP refers to the maximum amount
of power the cooling system is required to dissipate. This
option is set to Maximum by default.
NOTE:
This option is only available on certain SKUs of the
processors, and the number of alternative levels varies as
well.
th
Generation
th
Generation
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