Command Topology 1; Figure 30. Command Routing For Topology 1 - Intel 852GME Design Manual

R
6.3.4.1.

Command Topology 1

The command signal routing should transition from an external layer to an internal signal layer under
the GMCH/MCH. Keep to the same internal layer until transitioning back to an external layer
immediately prior to connecting the SO-DIMM0 connector pad. At the via transition for SO-DIMM0,
continue the signal route on the same internal layer to the series termination resistor (Rs), collocated to
SO-DIMM1. At this resistor the signal should transition to an external layer immediately prior to the pad
of Rs. After the series resistor, Rs, continue the signal route on the external layer landing on the
appropriate connector pad of SO-DIMM1. After SO-DIMM1, transition to the same internal layer or
stay on the external layer and route the signal to Rt.
Intel suggests that the parallel termination (Rt) be placed on both sides of the board to simplify routing
and minimize trace lengths. All internal and external signals should be ground referenced to keep the
path of the return current continuous.
Resistor packs are acceptable for the series and parallel command termination resistors but command
signals can not be placed within the same R-packs as data, strobe, or control signals. Figure 30 and
Table 26 below depict the recommended topology and layout routing guidelines for the DDR-SDRAM
command signals routing to SO-DIMM0 and SO-DIMM1.

Figure 30. Command Routing for Topology 1

GMCH
GMCH
Pin
The command signals should be routed using a 2 to 1 trace spacing to trace width ratio for signals within
the DDR group, except clocks and strobes. There should be a minimum of 20 mils spacing to non-DDR
related signals. Command signals should be routed on inner layers with minimized external traces.
® ®
Intel 852GME, Intel 852GMV and Intel
P1 L1
S0
SO-DIMM0 PAD
®
852PM Chipset Platforms Design Guide
System Memory Design Guidelines (DDR-SDRAM)
Rs
w
L2
L3
SO-DIMM1 PAD
Vtt
w
L4
Rt
S1
87