Secondary Ide Connector Requirements; Figure 56. Connection Requirements For Secondary Ide Connector - Intel 852GME Design Manual

I/O Subsystem
10.1.3.

Secondary IDE Connector Requirements

Figure 56. Connection Requirements for Secondary IDE Connector

Intel
ICH4-M
† Due to ringing,
PCIRST# must be
buffered
The following are connection requirements for Secondary IDE Connector:
22 - 47
each unique motherboard design, based on signal quality.
An 8.2 k - 10 k pull-up resistor is required on IRQ15 to VCC3_3.
A 4.7-k
Series resistors can be placed on the control and data lines to improve signal quality. The resistors
are placed as close to the connector as possible. Values are determined for each unique
motherboard design.
The 10-k resistor to ground on the PDIAG#/CBLID# signal is required on the Secondary
Connector. This change is to prevent the GPI pin from floating if a device is not present on the IDE
interface.
150
PCIRST# †
®
3.3V
4.7K
SIORDY (SRDSTB / SWDMARDY# )
IRQ[15]
GPIOy
10K
series resistors are required on RESET#. The correct value should be determined for
pull-up resistor to VCC3_3 is required on PIORDY and SIORDY.
® ®
Intel 852GME, Intel 852GMV and Intel
22 - 47
SDD[15:0]
SDA[2:0]
SDCS[3,1]#
SDIOR#
SDIOW#
SDDREQ
SDDACK#
8.2~10K
PDIAG# / CBLID#
®
852PM Chipset Platforms Design Guide
Ω
3.3V
CSEL
R