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Signal
PIN No.
XA[23:0]/
40~45
ExtMA[23:0]
47~51
54~60
63~68
XD[31:0]
75~79
81~87
89~94
96~102
106~112
nRCS[3:0]
69
72~74
nSCS
28
nECS[3:0]
29~32
nOE
37
nWE[3:0]/
33~36
ExtMnDB[3:0]
WorkCentre 385
Table 2: KS32C6100 Signal Descriptions
Type
I/O
The 24-bit address data bus, XA[23:0], acts as an output when
the ARM core or DMA is accessing the chip-select banks and
covers the full 16M-word (32-bit) address range of each ROM
and SRAM bank, and 64K-byte external I/O address range; or
it acts as an
input in external master mode and corresponds to ExtMA[23:0],
the lower 24 bits out of 28-bit external master address bus
ExtMA[27:0].
I/O
External bi-directional three-state 32-bit data bus. The
KS32C6100 data bus supports external 8-bit, 16-bit, and 32-bit
bus connection.
O
Not ROM chip select. The KS32C6100 can access up to four
external ROM banks.
nRCS0 corresponds to ROM bank 0, nRCS1 to bank 1, and so
on.
O
Not RSAM chip select. Selection to access external SRAM
bank.
O
Not external chip select. Four I/O banks are provided for mem-
ory-mapped external I/O operations, each of which contains up
to 16K bytes. The four nECS signals are used to select the four
I/O banks respectively.
O
Not data output enable for ROM/SRAM/External IO. Whenever
a memory access for ROM/SRAM/External IO occurs, the nOE
output controls the output enable port of the specific device.
O
Not data write enable for SRAM/External I/O. Whenever a
memory access for SRAM/External I/O occurs, the four nWE
outputs indicate the byte selections and control the write
enable port of the specific devices.
In external bus master mode, it acts as ExtMnDB[3:0] to indi-
cate the byte latch for external master accessing memory.
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Description
12/98
7 - 19
Circuit Description
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