Gate Drive; Typical Gate Drive Circuit; Gate Drive Propagation Delay And Dead Time - Siemens Vendor Manual

MicroHarmony Cell Sizes 40 - 260A Manual

5.4 Gate Drive

Four independent and optically isolated gate drive circuits provide the proper IGBT gate drive and out of saturation
feedback between the control and IGBTs.
5.4.1

Typical Gate Drive Circuit

P1, C1, and E1 connects to a blocking test circuit used for verifying IGBT operation at start up.
P1 and N1 connect to the isolated +28VDC gate drive power supply.
OOS1 is an isolated OOS signal that connects to the EPLD.
PC5 connects to a start-up hold off circuit which prevents firing until the SMPS is fully operational.
Q1 is the gate drive signal derived from the EPLD.
5.4.2

Gate Drive Propagation Delay and Dead Time

There is a time delay inherent to the gate drive circuit, from the time the EPLD tells the gate to turn on to the actual
time in which the gate does turn on. The turn on propagation delay should be no more than 1.1μSec. The turn off
propagation delay should be no more than 0.5μSec.
PWM dead time is 18.0 to 22.0 μS. This prevents the possibility of two devices in a pole from firing at the same time.
19001467: Version 1.0
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Cell Control Board - 10000432
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