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Communication Protocol
11.4 Error Handling
Several levels of error handling are implemented on the CCB in order to validate each message. The IMS C011
Transceiver provides the following inputs/outputs that are implemented as follows on the CCB:
QVALID
QACK
IVALID
IACK
RESET
11.5 Parity
The most significant data bit (bit 7) for each Modulator/CCB command/response message is used as an ODD parity
bit (i.e., 7 data bits + 1 parity bit result in an 8 bit data word with ODD parity).
The CCB parity check circuit generates a communication failure (COMFLT) if the parity is incorrect for more than
approximately 22 microseconds (i.e., 3 or more messages). Note that the 890485.02 GAL (U31) equations validate
parity for each received message.
11
11-2
Table 11-2: IMS C011 Status Indicators
Indicates that data on pins Q0-7 is valid (data from Master Link)
Input for CCB 'ACTIVITY' circuit that verifies message activity from Master Link
Generates CCB Communication fault (COMFLT) if 'ACTIVITY' fault exceeds
approximately 15 microseconds
'ACTIVITY' is validated for every message by the 890485.02 GAL
Generates Acknowledge Signal from CCB to Master Link IMS C011 that Q0-7 data
was read
Indicates that data on I0-7 is valid
Initiates transmission of CCB response to Master Link message approximately 1.2
μsec after QVALID received
Used as Latch Enable signal for CCB response data
Indicates that Acknowledge signal received from Master Link IMS C011 in
response to CCB transmission.
Reset circuit enabled 1.2 msec after a CCB Communication failure (COMFLT)
s
MicroHarmony Cell Sizes 40 - 260A Manual
19001467: Version 1.0
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