Omron SYSMAC CPM2B Operation Manual page 105

PLC Setup
Word(s) Bit(s)
DM 6651 00 to 07 Baud rate
00: 1,200 bps; 01: 2,400 bps; 02: 4,800 bps; 03: 9,600 bps; 04: 19,200 bps
08 to 15 Frame format
00:
01:
02:
03:
04:
05:
06:
07:
08:
09:
10:
11:
(Any other setting specifies standard settings (1 start bit, 7 data bits; even parity, 2 stop bits),
causes a non-fatal error, and turns ON AR 1302.)
DM 6652 00 to 15 Transmission delay (0000 to 9999 BCD sets a delay of 0 to 99,990 ms.)
(Any other setting specifies a delay of 0 ms, causes a non-fatal error, and turns ON AR 1302.)
DM 6653 00 to 07 Node number (Host Link)
00 to 31 (BCD)
(Any other setting specifies a node number of 00, causes a non-fatal error, and turns ON AR
1302.)
08 to 11 Start code selection for no-protocol communications
0: Disables start code; 1: Enables start code in DM 6654
(Any other setting disables the start code, causes a non-fatal error, and turns ON AR 1302.)
12 to 15 End code selection for no-protocol communications
0: Disables end code; 1: Enables end code in DM 6654; 2: Sets end code of CR, LF.
(Any other setting disables the end code, causes a non-fatal error, and turns ON AR 1302.)
DM 6654 00 to 07 Start code (00 to FF)
(This setting is valid only when bits 8 to 11 of DM 6653 are set to 1.)
08 to 15 When bits 12 to 15 of DM 6653 set to 0:
Sets the number of bytes to receive. (00: 256 bytes; 01 to FF: 1 to 255 bytes)
When bits 12 to 15 of DM 6653 set to 1:
Sets the end code. (00 to FF)
Error Log Settings (DM 6655)
The following settings are effective after transfer to the PLC.
DM 6655 00 to 03 Style
0: Shift after 7 records have been stored
1: Store only first 7 records (no shifting)
2 to F: Do not store records
04 to 07 Not used.
08 to 11 Cycle time monitor enable
0: Generate a non-fatal error for a cycle time that is too long.
1: Do not generate a non-fatal error.
12 to 15 Low battery error enable
0: Generate a non-fatal error for low battery voltage.
1: Do not generate a non-fatal error.
Low battery error detection is disabled (i.e., set to 1) by default in CPU Boards that do not have a
clock. If the PLC Setup is cleared, the setting will changed to 0 and a low battery error will occur.
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Start bits Data bits
1 bit 7 bits
1 bit 7 bits
1 bit 7 bits
1 bit 7 bits
1 bit 7 bits
1 bit 7 bits
1 bit 8 bits
1 bit 8 bits
1 bit 8 bits
1 bit 8 bits
1 bit 8 bits
1 bit 8 bits
Function
Stop bits Parity
1 bit Even
1 bit Odd
1 bit None
2 bits Even
2 bits Odd
2 bits None
1 bit Even
1 bit Odd
1 bit None
2 bits Even
2 bits Odd
2 bits None
Section 4-5
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