Sma Clock Connections; M24C02 2 Kb Iic Eeprom - Xilinx FMC XM101 LVDS QSE User Manual

5. SMA Clock Connections

Four SMA connectors (J2 - J5) are provided on the XM101 board.
The SMA to J1 FMC HPC connections are shown in
Table 1-13: SMA to FMC HPC Connections

6. M24C02 2 Kb IIC EEPROM

An STMicroelectronics M24C02 2 Kb serial IIC bus EEPROM (U3) component provides a
small amount of non-volatile memory storage on the XM101. The IIC interface is connected
directly to the board's IIC interface as shown in
The IIC address of this component is controlled by a combination of the board's interface
and chip enable connections to the component inputs on the XM101. Signals GA0 and GA1
from the board are connected to the chip enable inputs of the M24C02 component enables
E0 and E1. Xilinx boards provide GA0 and GA1 signal strapping to 3.3V and GND signals
creating different E0 and E1 chip enable decodes on the E1 and E0 inputs of the EEPROM.
The IIC memory addressing protocol requires a bus master to initiate communication to a
peripheral device using a start condition followed by a device select code. The device select
code consists of a 4 bit Device Type Identifier and a 3-bit Chip Enable Address (E2, E1 and
E0). Bit 0 is used to indicate read/write. The Device Type Identifier for the EEPROM is 1010
binary.
Device Code Select addresses of the EEPROM when the XM101 is connected to a Xilinx
board defined in
Table 1-14: EEPROM IIC Device Select Code
Bit 7:4 Device
Type Identifier
The M24C02 component data sheet is available online at www.st.com.
FMC XM101 User Guide
UG538 (v1.1) September 24, 2010
SMA
Net Name Pin Number
CLK1_M2C_P J2.1
CLK1_M2C_N J3.1
CLK3_M2C_P J4.1
CLK3_M2C_N J5.1
Table 1-14 defines the generic EEPROM Device Select Code as well as specific
Table 1-1, page
Bit 3 Bit 2
1010 0 GA0
www.xilinx.com
XM101 Board Technical Description
Table
J1 FMC
Connector
Pin Number
G2
G3
J2
J3
Figure 1-2, page
7.
Bit 1 Bit 0 LSB
Connected to mezzanine FMC HPC
GA1 Read/Write
interface
1-13.
10.
Description
21