Pmc And Lpd Mio; Mio Peripheral Mapping; Por_B Reset Circuit - Xilinx VCK190 Series User Manual

PMC and LPD MIO

The following table provides MIO peripheral mapping implemented on the VCK190 board. See
the Versal ACAP Technical Reference Manual (AM011) for more information on MIO peripheral
mapping. The XCVC1902 ACAP Bank 500, 501, and 502 mappings are listed in the table.
Table 7: MIO Peripheral Mapping
PMC MIO[0:25] Bank 500
0 MIO CONN. J212
1 MIO CONN. J212
2 MIO CONN. J212
3 MIO CONN. J212
4 MIO CONN. J212
5 MIO CONN. J212
6 MIO CONN. J212
7 MIO CONN. J212
8 MIO CONN. J212
9 MIO CONN. J212
10 MIO CONN. J212
11 MIO CONN. J212
12 MIO CONN. J212
13 U103.6 USB3320 U99 reset gate
14 USB3320 U99
15 USB3320 U99
16 USB3320 U99
17 USB3320 U99
18 USB3320 U99
UG1366 (v1.0) January 7, 2021
VCK190 Board User Guide
Figure 8: POR_B Reset Circuit
PMC MIO[26:51] Bank 501
26 SD1
27 SD1
28 SD1
29 SD1
30 SD1
31 SD1
32 SD1
33 SD1
34 SD1
35 SD1
36 SD1
37 ZU4_TRIGGER
38 PCIE_PERST_B
39 PCIE_PWRBRK_B
40 CAN1_TXD
41 CAN1_RXD
42 UART0
43 UART0
44 I2C1
Chapter 3: Board Component Descriptions
LPD MIO[0:25] Bank 502
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
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