Fmcp1 Connector J51; Fmcp2 Connector J53 - Xilinx VCK190 Series User Manual

• 239 ground and 17 power connections
For more information about the VITA 57.4 FMC+ specification, see the
Alliance website.

FMCP1 Connector J51

[Figure 3, callout 20]
The HSPC connector J51 implements a subset of the full FMCP connectivity:
• 68 single-ended or 34 differential user-defined pairs (34 LA pairs: LA[00:33])
• 12 transceiver differential pairs
• 3 transceiver differential clocks
• 2 differential clocks
• 239 ground and 15 power connections

FMCP2 Connector J53

[Figure 3, callout 20]
The HSPC connector J53 implements a subset of the full FMCP connectivity:
• 68 single-ended or 34 differential user-defined pairs (34 LA pairs: LA[00:33])
• 12 transceiver differential pairs
• 3 transceiver differential clocks
• 2 differential clocks
• 1 differential (REFCLK) clock C2M pair
• 1 differential (SYNC) clock C2M pair
• 239 ground and 15 power connections
See the FPGA Mezzanine Card (FMC)
FMCP HSPC connector. The detailed ACAP connections for the feature described in this section
are documented in the VCK190 board XDC file, referenced in
Constraints.
UG1366 (v1.0) January 7, 2021
VCK190 Board User Guide
Chapter 3: Board Component Descriptions
VITA 57.4 specification
VITA FMC Marketing
for additional information on the
Appendix B: Xilinx Design
www.xilinx.com
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