Ddr4 Udimm Socket; Ddr4 Dimm Memory - Xilinx VCK190 Series User Manual

Table 6: I/O Voltage Rails (cont'd)
ACAP (U1)
Bank
XPIO Bank 703
XPIO Bank 704
XPIO Bank 705
XPIO Bank 706
XPIO Bank 707
XPIO Bank 708
XPIO Bank 709
XPIO Bank 710
XPIO Bank 711
PMC MIO 500
PMC MIO 501
LP MIO 502

DDR4 UDIMM Socket

[Figure 3, callout 1]
The VCK190 board XPIO triplet 1 (banks 700/701/702) memory interface supports 288-pin 72-
bit DDR4 DIMM socket J45.
The VCK190 board is shipped with a DDR4 UDIMM installed:
• Manufacturer: Micron
UG1366 (v1.0) January 7, 2021
VCK190 Board User Guide
Power Supply Rail
Voltage
Net Name
VCC1V1_LP4 1.1V
VCC1V1_LP4 1.1V
VCC1V1_LP4 1.1V
VADJ_FMC 1.5V
VADJ_FMC 1.5V
VADJ_FMC 1.5V
VCC1V1_LP4 1.1V
VCC1V1_LP4 1.1V
VCC1V1_LP4 1.1V
VCCO_500 3.3V
VCCO_501 3.3V
VCCO_502 3.3V
Figure 6: DDR4 DIMM Memory
700
DDR4 72-bit
Chapter 3: Board Component Descriptions
LPDDR4_3_DQ[0:7, 16:23], ADDR/CTRL
LPDDR4_2_DQ[0:7, 16:23]; LPDDR4_3_DQ[8:15, 24:31]
LPDDR4_2_DQ[8:15, 24:31], ADDR/CTRL; Si570 U3 200 MHz
8A34001_GPIO_[0:15]; FMCP1_LA[00:16]
FMCP1_LA[17:33]; FMCP2_LA[26:33]
FMCP2_LA[00:25]
LPDDR4_1_DQ[0:7, 16:23], ADDR/CTRL
LPDDR4_0_DQ[0:7, 16:23]; LPDDR4_1_DQ[8:15, 24:31]
LPDDR4_0_DQ[8:15, 24:31], ADDR/CTRL; Si570 U4 200 MHz
SYSMON IF; PMC_MIO[0:25]_500; ISL60002 U6 1.042V VREF;
J1 2x6 SYSMON PIN HDR
PMC_MIO[26:51]
LPD_MIO[0:25]
XPIO
Triplet 1
701 702
UDIMM
X23197-120120
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