Xilinx VCK190 Series User Manual page 29

Table 7: MIO Peripheral Mapping (cont'd)
PMC MIO[0:25] Bank 500
19 USB3320 U99
20 USB3320 U99
21 USB3320 U99
22 USB3320 U99
23 USB3320 U99
24 USB3320 U99
25 USB3320 U99
PMC MIO[0–12] Bank 500: MIO Daughter Card (DC)
Connector J212
[Figure 3, callout 5]
The VCK190 U1 XCVC1902 bank 500 PMC_MIO[0:12] pins are connected to the 240-pin (8 x
30) MIO connector J212. This interface enables high-speed XCVC1902 configuration using the
X-EBM-01 QSPI external daughter card installed on J212.
The detailed ACAP connections for the feature described in this section are documented in the
VCK190 board XDC file, referenced in
MIO connector J212 pinout is listed in the following figure.
UG1366 (v1.0) January 7, 2021
VCK190 Board User Guide
Chapter 3: Board Component Descriptions
PMC MIO[26:51] Bank 501
45 I2C1
46 I2C0
47 I2C0
48 GEM0
49 GEM1
50 PCIE_WAKE_B
51 SD1
Appendix B: Xilinx Design
LPD MIO[0:25] Bank 502
19 GEM1
20 GEM1
21 GEM1
22 GEM1
23 GEM1
24 GEM0, GEM1
25 GEM0, GEM1
Constraints. The XCVC1902
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