Spi Configuration: Mcbsp As The Master; Configuration: Mcbsp As The Slave; Spi-Mode Clock Stop Scheme - Texas Instruments TMS320C6000 DSP Reference Manual

DX Enabler: DXENA
The clock stop mode (CLKSTP) of the McBSP provides compatibility with the SPI protocol. The McBSP
supports two SPI transfer formats that are specified by the clock stop mode bits (CLKSTP) in SPCR. The
CLKSTP bits in conjunction with the CLKXP bit in PCR allows serial clocks to be stopped between
transfers using one of four possible timing variations, as shown in
show the timing diagrams of the two SPI transfer formats and the four timing variations.
Note: The digital loopback mode (DLB = 1 in SPCR cannot be used in conjunction with the
clock stop mode (CLKSTP = 1x).)
CLKSTP Bits
0X
10
11
10
11
70 SPI Protocol: CLKSTP
Figure 9-1. SPI Configuration: McBSP as the Master
McBSP master
CLKX
DX
DR
FSX
Figure 9-2. Configuration: McBSP as the Slave
McBSP slave
CLKX
DX
DR
FSX
Table 9-1. SPI-Mode Clock Stop Scheme
CLKXP Bit Clock Scheme
X Clock stop mode is disabled. Clock is enabled for non-SPI mode.
0 Low inactive state without delay. The McBSP transmits data on the rising edge of CLKX
and receives data on the falling edge of CLKX.
0 Low inactive state with delay. The McBSP transmits data one-half cycle ahead of the rising
edge of CLKX and receives data on the rising edge of CLKX.
1 High inactive state without delay. The McBSP transmits data on the falling edge of CLKX
and receives data on the rising edge of CLKX.
1 High inactive state with delay. The McBSP transmits data one-half cycle ahead of the
falling edge of CLKX and receives data on the falling edge of CLKX.
SPI compliant
slave
SCK
MOSI
MISO
SS
SPI compliant
master
SCK
MISO
MOSI
SS
Table 9-1. Figure 9-3
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and Figure 9-4
SPRU580E – December 2005