Texas Instruments AFE79 Series Programming & User Manual page 395

www.ti.com
Bit Field
7-5 0
FB_ROOT_CLK_DI
4-0
V_M
2.5.31 Register 45h (offset = 45h) [reset = 2h]
7 6
0 0
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit Field
7-5 0
FB_ROOT_CLK_DI
4-0
V_N_M1
2.5.32 Register 46h (offset = 46h) [reset = 1h]
7 6
0 0
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit Field
7-5 0
DDC_RD_CLK_RX
4-0
1_DIV_M
2.5.33 Register 47h (offset = 47h) [reset = 0h]
7 6
0 0
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Bit Field
7-5 0
DDC_RD_CLK_RX
4-0
1_DIV_N_M1
SBAU337 – May 2020
Submit Documentation Feedback
Table 2-531. Register 44 Field Descriptions
Type Reset
R/W 0h
R/W 2h
Figure 2-527. Register 45h
5 4
0
R/W-0h
Table 2-532. Register 45 Field Descriptions
Type Reset
R/W 0h
R/W 2h
Figure 2-528. Register 46h
5 4
0
R/W-0h
Table 2-533. Register 46 Field Descriptions
Type Reset
R/W 0h
R/W 1h
Figure 2-529. Register 47h
5 4
0
R/W-0h
Table 2-534. Register 47 Field Descriptions
Type Reset
R/W 0h
R/W 0h
Copyright © 2020, Texas Instruments Incorporated
Description
Must read or write 0
M value of root divider.
Output of this divider goes to ddc and jesd clock dividers
3 2
FB_ROOT_CLK_DIV_N_M1
R/W-2h
Description
Must read or write 0
N value of root divider.
Output of this divider goes to ddc and jesd clock dividers
3 2
DDC_RD_CLK_RX1_DIV_M
R/W-1h
Description
Must read or write 0
M value of ddc divider.
Output of this divider, clock frequency should match the
RXA/RXC interface rate
3 2
DDC_RD_CLK_RX1_DIV_N_M1
R/W-0h
Description
Must read or write 0
N-1 value of ddc divider.
Output of this divider, clock frequency should match the
RXA/RXC interface rate
Serial Interface Register Maps
ADC JESD Register Map
1 0
1 0
1 0
395