AMD AM186EM User Manual page 43

SRDY Synchronous Ready (input, synchronous, level-sensitive)
This pin indicates to the microcontroller that the addressed memory
space or I/O device will complete a data transfer. The SRDY pin accepts
an active-High input synchronized to CLKOUTA. Using SRDY instead
of ARDY allows a relaxed system timing because of the elimination of
the one-half clock period required to internally synchronize ARDY. To
always assert the ready condition to the microcontroller, tie SRDY High.
If the system does not use SRDY, tie the pin Low to yield control to
ARDY.
TMRIN0 Timer Input 0 (input, synchronous, edge-sensitive)
This pin supplies a clock or control signal to the internal microcontroller
timer 0. After internally synchronizing a Low-to-High transition on
TMRIN0, the microcontroller increments the timer. TMRIN0 must be
tied High if not being used.
TMRIN1 Timer Input 1 (input, synchronous, edge-sensitive)
This pin supplies a clock or control signal to the internal microcontroller
timer 1. After internally synchronizing a Low-to-High transition on
TMRIN1, the microcontroller increments the timer. TMRIN1 must be
tied High if not being used.
TMROUT0 Timer Output 0 (output, synchronous)
This pin supplies to the system either a single pulse or a continuous
waveform with a programmable duty cycle. TMROUT0 is floated during
a bus hold or reset.
TMROUT1 Timer Output 1 (output, synchronous)
This pin supplies to the system either a single pulse or a continuous
waveform with a programmable duty cycle. It can also be programmed
as a watchdog timer. TMROUT1 is floated during a bus hold or reset.
TXD Transmit Data (output, asynchronous)
This pin supplies asynchronous serial transmit data from the
microcontroller UART to the system.
UCS/ONCE1 Upper Memory Chip Select (output, synchronous)
ONCE Mode Request 1 (input, internal pullup)
UCS—This pin indicates to the system that a memory access is in
progress to the upper memory block. The base address and size of the
upper memory block are programmable up to 512 Kbytes. UCS is held
High during a bus hold condition.
After power-on reset, UCS is asserted because the processor begins
executing at FFFF0h and the default configuration for the UCS chip
select is 64 Kbytes from F0000h to FFFFFh. See section 5.5.1.
ONCE1—During reset this pin and ONCE0 indicate to the
microcontroller the mode in which it should operate. ONCE0 and
ONCE1 are sampled on the rising edge of RES. If both pins are asserted
Low, the microcontroller enters ONCE mode; otherwise, it operates
normally. In ONCE mode, all pins assume a high-impedance state and
remain in that state until a subsequent reset occurs. To guarantee that
the microcontroller does not inadvertently enter ONCE mode, ONCE1
has a weak internal pullup resistor that is active only during a reset.
System Overview
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