AMD AM186EM User Manual page 177

WD (Virtual Watchdog Timer Interrupt InService) 7-
22
WD (Virtual Watchdog Timer Interrupt Mask) 7-24
WD (Virtual Watchdog Timer Interrupt Request) 7-
21
WLGN (Word Length) 10-3
BRK bit (Send Break) 10-2
BRKI bit (Break Interrupt) 10-4
BRKVAL bit (Break Value) 10-2
C
C bit (Cascade Mode) 7-13
CAD bit (CLKOUTA Drive Disable) 4-7
CAF bit (CLKOUTA Output Frequency) 4-7
Cascade mode 7-10
CBD bit (CLKOUTB Drive Disable) 4-7
CBF bit (CLKOUTB Output Frequency) 4-7
CHG bit (Change Start Bit) 9-4
CLKDIV2 signal (Clock Divide by 2)
definition 3-12
CLKOUTA signal (Clock Output A)
definition 3-3
CLKOUTB signal (Clock Output B)
definition 3-4
Clock Prescaler Register
description 6-2
CONT bit (Continuous Mode Bit)
Timer 0 Mode/Control Register 8-4
Timer 1 Mode/Control Register 8-4
Timer 2 Mode/Control Register 8-5
D
D1-D0 field (DMA Channel Interrupt InService) 7-22, 7-
32, 7-34
D1-D0 field (DMA Channel Interrupt Masks) 7-24
D1-D0 field (DMA Channel Interrupt Request) 7-21, 7-
31
DDA15-DDA0 field (DMA Destination Address Low) 9-7
DDA19-DDA16 field (DMA Destination Address High)
9-6
DDEC bit (Destination Decrement) 9-3
DE0 bit (SDEN0 Enable) 11-4
DE1 bit (SDEN1 Enable) 11-4
DEN signal (Data Enable)
definition 3-4
development tools
thirdparty products xiv
DHLT bit (DMA Halt) 7-20, 7-30
DINC bit (Destination Increment) 9-3
DM/IO bit (Destination Address Space Select) 9-3
DMA 0 Control Register
description 9-3
DMA 0 Destination Address High Register
description 9-6
DMA 0 Destination Address Low Register
description 9-7
DMA 0 Interrupt Control Register
description
Master mode 7-17
Slave mode 7-29
DMA 0 Source Address High Register
description 9-8
DMA 0 Source Address Low Register
description 9-9
DMA 0 Transfer Count Register
description 9-5
DMA 1 Control Register
description 9-3
DMA 1 Destination Address High Register
description 9-6
DMA 1 Destination Address Low Register
description 9-7
DMA 1 Interrupt Control Register
description
Master mode 7-17
Slave mode 7-29
DMA 1 Source Address High Register
description 9-8
DMA 1 Source Address Low Register
description 9-9
DMA 1 Transfer Count Register
description 9-5
documentation
AMD E86 Family publications xiv
ordering documentation and literature iii
DR/DT bit (Data Receive/Transmit Complete) 11-3
DRQ1-DRQ0 signals (DMA Requests)
definition 3-4
DSA15-DSA0 field (DMA Source Address Low) 9-9
DSA19-DSA16 field (DMA Source Address High) 9-8
DT/R signal (Data Transmit or Receive)
definition 3-4
Index
I-3