AMD AM186EM User Manual page 36

INT3/INTA1/IRQ
INT4
LCS/ONCE0
3-6
Maskable Interrupt Request 3 (input, asynchronous)
Interrupt Acknowledge 1 (output, synchronous)
Slave Interrupt Request (output, synchronous)
INT3—This pin indicates to the microcontroller that an interrupt request
has occurred. If the INT3 pin is not masked, the microcontroller then
transfers program execution to the location specified by the INT3 vector
in the microcontroller interrupt vector table. Interrupt requests are
synchronized internally, and they can be edge-triggered or level-
triggered. To guarantee the interrupt is recognized, the device issuing
the request must continue asserting INT3 until the request is
acknowledged. INT3 becomes INTA1 when INT1 is configured in
cascade mode.
INTA1—When the microcontroller interrupt control unit is operating in
cascade mode, this pin indicates to the system that the microcontroller
needs an interrupt type to process the interrupt request on INT1. The
peripheral issuing the interrupt request must provide the microcontroller
with the corresponding interrupt type.
IRQ—When the microcontroller interrupt control unit is operating as a
slave to an external master interrupt controller, this pin lets the
microcontroller issue an interrupt request to the external master
interrupt controller.
Maskable Interrupt Request 4 (input, asynchronous)
This pin indicates to the microcontroller that an interrupt request has
occurred. If the INT4 pin is not masked, the microcontroller then
transfers program execution to the location specified by the INT4 vector
in the microcontroller interrupt vector table. Interrupt requests are
synchronized internally, and they can be edge-triggered or level-
triggered. To guarantee the interrupt is recognized, the device issuing
the request must continue asserting INT4 until the request is
acknowledged.
Lower Memory Chip Select (output, synchronous, internal pullup)
ONCE Mode Request 0 (input)
LCS—This pin indicates to the system that a memory access is in
progress to the lower memory block. The base address and size of the
lower memory block are programmable up to 512 Kbytes. LCS is held
High during a bus hold condition.
ONCE0—During reset this pin and UCS/ONCE1 indicate to the
microcontroller the mode in which it should operate. ONCE0 and
ONCE1 are sampled on the rising edge of RES. If both pins are asserted
Low, the microcontroller enters ONCE mode; otherwise, it operates
normally.
In ONCE mode, all pins assume a high-impedance state and remain in
that state until a subsequent reset occurs. To guarantee that the
microcontroller does not inadvertently enter ONCE mode, ONCE0 has
a weak internal pullup resistor that is active only during a reset.
System Overview