AMD AM186EM User Manual page 171

Figure A-1 Internal Register Summary (continued)
15
34
DMA 0 Interrupt Control Register (DMA0CON)
Master Mode—Page 7-17
Slave Mode—Page 7-29
15
32
Timer Interrupt Control Register (TCUCON)
Master Mode—Page 7-17
Timer 0 Interrupt Control Register (T0INTCON)
Slave Mode—Page 7-29
15
30
DHLT
Interrupt Status Register (INTSTS)
Master Mode—Page 7-20
Slave Mode—Page 7-30
15
2E
Interrupt Request Register (REQST)
Master Mode
Page 7-21
15
2E
Interrupt Request Register (REQST)
Slave Mode
Page 7-31
Reserved
Reserved
Reserved SPI
Reserved
Register Summary
7
7
7
Reserved
7
WD I4 I3 I2 I1
7
TMR2
0
MSK PR2–PR0
0
MSK PR2–PR0
0
TMR2–TMR0
0
I0 D1 D0 Res TMR
0
D1 D0 Res
TMR1 TMR0
A-13